Semiconductor memory circuit with improved serial access circuit arrangement

Claim 2

A semiconductor memory circuit comprising; first and second memory planes separate from each other, each of said first and second memory planes including first and second memory arrays separate from each other, each of said first and second memory arrays having a plurality of word lines consecutively arranged in a first number of rows, a plurality of bit lines arranged in a second number of consecutive columns and a plurality of memory cells coupled to the word lines and the bit lines, a plurality of latch circuits of said second number, each of said latch circuits having an input end and an output end and storing data applied to the input end thereof, a plurality of first transfer circuits of said second number coupled between the bit lines in said second number of columns of said first memory array and the input ends of said latch circuits of said second number for operatively establishing signal paths therebetween, respectively, a plurality of second transfer circuits coupled between the bit lines in the second number of columns of said second memory array and the input ends of said latch circuits of said second number for operatively establishing signal paths therebetween, respectively, a first data line, a plurality of third transfer circuits of said second number connected between the output ends of said latch circuits and said first data line, respectively, a serial selection circuit coupled to said third transfer circuits for selectively enabling said third transfer circuits one by one in sequence, a first row decoder for operatively selecting one of the word lines of said first memory array, and a second row decoder for operatively selecting one of the word lines of said second memory array, a first selection circuit for enabling said first row decoders of said first and second memory planes simultaneously in a first mode and enabling said second row decoders of said first and second memory planes simultaneously in a second mode, and a second selection circuit for enabling said first transfer circuits of said first and second memory planes simultaneously in said first mode and enabling said second transfer circuits of said first and second memory planes simultaneously in said second mode.

Claim 3

The memory circuit according to claim 1, in which each of said first and second memory arrays further includes a plurality of sense amplifiers of said second number provided for the columns thereof.

Claim 4

The memory circuit according to claim 1, wherein said first selection circuit includes a decoder receiving at least one row address signal.

Claim 5

The memory circuit according to claim 1, in which each of said first and second transfer circuits includes a sense amplifier and a transfer gate connected to said sense amplifier.

Claim 6

The memory circuit according to claim 1, in which each of said first and second memory planes further includes second and third data lines, a plurality of first column transfer gates of said second number coupled between the bit lines of the first memory array thereof and said second data line, a plurality of second transfer gates coupled between the bit lines of the second memory array thereof and said third data line, and a column decoder for selecting one of said first column transfer gates and one of said second column transfer gates.

Claim 7

A semiconductor memory circuit comprising; first and second memory arrays separate from each other, each of said first and second memory arrays including a first number of word lines, a second number of bit lines intersecting with said word lines and a plurality of memory cells coupled to said word lines and bit lines, a plurality of latch circuits of said second number, each of said latch circuits having an input end and an output end and storing a data signal applied to the input end thereof, a plurality of first transfer circuits of said second number coupled between the bit lines of said first memory array and the input ends of said latch circuits for operatively transferring signals at said bit lines of said first memory array to said input ends of said latch circuits, respectively, a plurality of second transfer circuits of said second number coupled between the bit lines of said second memory array and the input ends of said latch circuit for operatively transferring signals at the bit lines of said second memory array to the input ends of said latch circuits, respectively, a first row decoder for operatively selecting one of the word lines of said first memory array, a second row decoder for operatively selecting one of the word lines of said second memory array, a first data line, a plurality of first selection switches of said second number connected between the output ends of said latch circuits and said first data line, respectively, a serial selection circuit for selecting said first selection switches one by one in sequence thereby to serially transfer signals at the output ends of said latch circuits to said first data line, a second data line, a plurality of second selection switches of said second number connected between the bit lines of said first memory array and said second data line, respectively, a third data line, a plurality of third selection switches of said second number connected between the bit lines of said second memory array and said third data line, respectively, a column decoder for selectively enabling one of said second selection switches and one of said third selection switches, first control means for selectively enabling one of said first and second row decoders, second control means for enabling said first transfer circuits when said first row decoder is enabled and enabling said second transfer circuits when said second row decoder is enabled, a serial port coupled to said first data line, a first random access port coupled to said second data line and a second random access port coupled to said third data line.

Claim 8

A semiconductor memory circuit comprising; first and second memory arrays separate from each other, each of said first and second memory arrays including a first number of word lines, a second number of bit lines intersecting with said word lines and a plurality of memory cells coupled to said word lines and bit lines, a plurality of latch circuits of said second number, each of said latch circuits having an input end and an output end and storing a data signal applied to the input end thereof, a plurality of first transfer circuits of said second number coupled between the bit lines of said first memory array and the input ends of said latch circuits for operatively transferring signals at said bit lines of said first memory array to said input ends of said latch circuits, respectively, a plurality of second transfer circuits of said second number coupled between the bit lines of said second memory array and the input ends of said latch circuit for operatively transferring signals at the bit lines of said second memory array to the input ends of said latch circuits, respectively, a first row decoder for operatively selecting one of the word lines of said first memory array, a second row decoder for operatively selecting one of the word lines of said second memory array, a first data line, a plurality of first selection switches of said second number connected between the output ends of said latch circuits and said first data line, respectively, a serial selection circuit for selecting said first selection switches one by one in sequence thereby to serially transfer signals at the output ends of said latch circuits to said first data line, a second data line, a plurality of second selection switches of said second number connected between the bit lines of said first memory array and said second data line, respectively, a third data line, a plurality of third selection switches of said second number connected between the bit lines of said second memory array and said third data line, respectively, a column decoder for selectively enabling one of said second selection switches and one of said third selection switches, first control means for selectively enabling one of said first and second row decoders, second control means for enabling said first transfer circuits when said first row decoder is enabled and enabling said second transfer circuits when said second row decoder is enabled, a serial port coupled to said first data line, a first random access port coupled to said second data line and a second random access port coupled to said third data line.

Claim 9

The memory circuit according to claim 6, in which each of said first and second transfer circuits includes a sense amplifier having an input end coupled to one of the bit lines and an output end, and a transfer gate coupled between the output end of said sense amplifier and the input end of the associated latch circuit.