US6067244A
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Ferroelectric dynamic random access memory
Assignee: Yale University
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Filing: 1998-09-16
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Granted: 2000-05-23
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Expires: 2018-09-16
Abstract
Abstract A memory including an array of memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element; and sense and refresh circuitry connected to the array of memory cells to read stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and to refresh the stored data.
Inventors
- 👤 Tso-Ping Ma
- 👤 Jin-Ping Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/223; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
84 words
A memory comprising: an array of volatile memory cells, each of which includes as its memory element a ferroelectric field effect transistor (FET) which stores information in a polarization state that decays over time; and sense and refresh circuitry connected to the array of volatile memory cells and which during operation repeatedly reads stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and refreshes the stored data by restoring the ferroelectric Polarization state of the ferroelectric FETs of each cell.
Claim 2
Dependent Claim
84 words
A memory comprising: an array of volatile memory cells, each of which includes as its memory element a ferroelectric field effect transistor (FET) which stores information in a polarization state that decays over time; and sense and refresh circuitry connected to the array of volatile memory cells and which during operation repeatedly reads stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and refreshes the stored data by restoring the ferroelectric Polarization state of the ferroelectric FETs of each cell.
Claim 3
Dependent Claim
25 words
The memory of claim 1 wherein said sense and refresh circuitry is programmed to periodically refresh the stored data in the array of memory cells.
Claim 4
Dependent Claim
55 words
The memory of claim 1 wherein said sense and refresh circuitry is programmed to periodically sense the stored data in a selected one of the memory cells and if the sensed data in the selected memory cell has decayed to below a threshold value to automatically refresh the data stored in the selected memory cell.
Claim 5
Dependent Claim
29 words
The memory of claim 1 wherein each memory cell in the array of memory cells further comprises a select transistor connected to the ferroelectric FET in that memory cell.
Claim 6
Dependent Claim
32 words
The memory of claim 4 wherein in each memory cell in the array of memory cells, the select transistor is connected to a gate of the ferroelectric FET in that memory cell.
Claim 7
Dependent Claim
36 words
The memory of claim 4 wherein in each memory cell in the array of memory cells, the select transistor is connected to one of a source and drain of the ferroelectric FET in that memory cell.
Claim 8
Dependent Claim
27 words
The memory of claim 1 wherein in each memory cell of the array of memory cells, the ferroelectric transistor includes a gate dielectric made of ferroelectric material.
Claim 9
Dependent Claim
38 words
The memory of claim 1 wherein in each memory cell of the array of memory cells, the ferroelectric transistor includes a gate dielectric stack made up of a layer of ferroelectric material and a layer of dielectric material.
Claim 10
Dependent Claim
34 words
The memory of claim 8 wherein in each memory cell of the array of memory cells, the layer of dielectric material lies between the ferroelectric material and a channel region in the ferroelectric transistor.
Claim 11
Dependent Claim
40 words
The memory of claim 1 wherein in each memory cell of the array of memory cells, the ferroelectric transistor includes a gate dielectric stack made up of a layer of ferroelectric material and first and second layers of dielectric material.
Claim 12
Dependent Claim
30 words
The memory of claim 10 wherein in each memory cell of the array of memory cells, the ferroelectric material is sandwiched between the first and second layers of dielectric material.
Claim 13
Dependent Claim
29 words
The memory of claim 1 wherein said sense and refresh circuitry is structured to non-destructively read stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor.
Claim 14
Dependent Claim
67 words
A DRAM comprising: an array of volatile memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element and which stores information as a ferroelectric polarization state, wherein the DRAM determines a stored value within any given memory cell by non-destructively sensing source-to-drain conductivity of the corresponding ferroelectric FET, and wherein the memory elements are volatile because the ferroelectric polarization state decays.
Claim 15
Dependent Claim
67 words
A DRAM comprising: an array of volatile memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element and which stores information as a ferroelectric polarization state, wherein the DRAM determines a stored value within any given memory cell by non-destructively sensing source-to-drain conductivity of the corresponding ferroelectric FET, and wherein the memory elements are volatile because the ferroelectric polarization state decays.
Claim 16
Dependent Claim
20 words
The DRAM of claim 13 wherein the determination of the stored value within any given memory cell is done non-destructively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |