US5528535A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Renesas Electronics Corp
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Filing: 1995-03-07
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Granted: 1996-06-18
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Expires: 2015-03-07
Abstract
Abstract A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.
Inventors
- 👤 Shigeru Honjo
- 👤 Kazumasa Yanagisawa
- 👤 Kiyoshi Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:19
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
201 words
A semiconductor memory device comprising: a memory matrix made up of memory cells arranged in matrix, each memory cell having a ferroelectric capacitor and an address selection MOSFET; a plurality of memory blocks into which the memory matrix is divided every one or more word lines; mode storage circuits provided in one-to-one correspondence for the memory blocks, the mode storage circuits storing a DRAM mode or an NV (non-volatile mode) mode; refresh operation count circuits for counting the number of refresh operations performed consecutively for each memory block; a mode change circuit which, during an n-th refresh operation (where n is a predetermined number of times), makes a memory access to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and switches the mode storage circuit from the DRAM mode to the NV mode, the mode change circuit switching the mode storage circuit from the NV mode to the DRAM mode during a read or write operation on a memory cell in the memory block; and a mode decision circuit which omits the refresh operation on the memory block that was switched to the NV mode according to the stored information in the mode storage circuit.
Claim 2
Dependent Claim
201 words
A semiconductor memory device comprising: a memory matrix made up of memory cells arranged in matrix, each memory cell having a ferroelectric capacitor and an address selection MOSFET; a plurality of memory blocks into which the memory matrix is divided every one or more word lines; mode storage circuits provided in one-to-one correspondence for the memory blocks, the mode storage circuits storing a DRAM mode or an NV (non-volatile mode) mode; refresh operation count circuits for counting the number of refresh operations performed consecutively for each memory block; a mode change circuit which, during an n-th refresh operation (where n is a predetermined number of times), makes a memory access to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and switches the mode storage circuit from the DRAM mode to the NV mode, the mode change circuit switching the mode storage circuit from the NV mode to the DRAM mode during a read or write operation on a memory cell in the memory block; and a mode decision circuit which omits the refresh operation on the memory block that was switched to the NV mode according to the stored information in the mode storage circuit.
Claim 3
Dependent Claim
46 words
A semiconductor memory device according to claim 1, wherein the memory blocks are divided for each word line used for the refresh operation, and the mode storage circuit is formed of a static memory having storage bits, each corresponding to one of the individual word lines.
Claim 4
Dependent Claim
91 words
A semiconductor memory device according to claim 2, wherein the refresh operation count circuit comprises: a memory circuit made up of a plurality of memory cells and sharing the word lines with the memory matrix; and a control circuit which, at each word line selection performed by the refresh operation, adds +1 to data read from the memory circuit and restores the result into the memory cell of the memory circuit and, at each word line selection performed by the read or write operation, resets stored information in the memory circuit.
Claim 5
Dependent Claim
20 words
A semiconductor memory device according to claim 3, wherein an external input interface is made compatible with a dynamic RAM.
Claim 6
Dependent Claim
20 words
A semiconductor memory device according to claim 3, wherein an external input interface is made compatible with a static RAM.
Claim 7
Dependent Claim
50 words
A semiconductor memory device according to claim 5, wherein in the same way that the memory blocks are divided, a plate is also divided so that only the corresponding plate is temporarily changed to a power supply voltage at time of switching from the DRAM mode to the NV mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |