Non-destructive readout ferroelectric memory cell

Claim 2

A memory cell comprising: a) means for storing a bit of information, said means having two terminals and said means being adapted to store information in response to an electrical signal applied between the two terminals; b) means for sensing the value of the bit of information in the storing means, said means comprising (i) means for applying a voltage of a first polarity to the storing means; (ii) means for producing an indication of the value of the bit at a time t 1 after the voltage is applied to the storing means; and (iii) means, responsive to the sensing means, for changing the polarity of the voltage applied to the storing means when the bit of information has a predetermined value, said means operating to change the polarity at the time t 1 after the voltage is applied by the sensing means.

Claim 3

The memory of claim 1 wherein the storing means comprises a ferroelectric cell having two terminals.

Claim 4

A memory cell having a first terminal and a second terminal comprising: a) means, comprising a ferroelectric cell having a first terminal and a second terminal, for storing a bit of information, said means being adapted to store information in response to an electrical signal applied between the two terminals; and b) means for changing the polarity of the electrical signal applied between the two terminals in response to the bit of information in the storing means, said means comprising: (i) a first transistor switch connected between the first terminal of the memory cell and the first terminal of the ferroelectric cell, said first transistor switch having a control electrode; (ii) a second transistor switch connected between the second terminal of the ferroelectric cell and the first terminal of the memory cell, said second transistor switch having a control electrode; (iii) a third transistor switch connected between the first terminal of the ferroelectric cell and the second terminal of the memory cell, said third transistor switch having a control electrode; (iv) a fourth transistor switch connected between the second terminal of the ferroelectric cell and the second terminal of the memory cell, said fourth transistor switch having a control electrode; and (v) means for providing control inputs to the control electrodes of the first, second, third and fourth transistor switches, said control inputs to the first and fourth transistor switches being in a first state while the control inputs to the second and third transistor switches are in a second state.

Claim 5

A memory cell having a first terminal and a second terminal comprising: a) means, comprising a ferroelectric cell having a first terminal and a second terminal, for storing a bit of information, said means being adapted to store information in response to an electrical signal applied between the two terminals; and b) means for changing the polarity of the electrical signal applied between the two terminals in response to the bit of information in the storing means, said means comprising: (i) a first transistor switch connected between the first terminal of the memory cell and the first terminal of the ferroelectric cell, said first transistor switch having a control electrode; (ii) a second transistor switch connected between the second terminal of the ferroelectric cell and the first terminal of the memory cell, said second transistor switch having a control electrode; (iii) a third transistor switch connected between the first terminal of the ferroelectric cell and the second terminal of the memory cell, said third transistor switch having a control electrode; (iv) a fourth transistor switch connected between the second terminal of the ferroelectric cell and the second terminal of the memory cell, said fourth transistor switch having a control electrode; and (v) means for providing control inputs to the control electrodes of the first, second, third and fourth transistor switches, said control inputs to the first and fourth transistor switches being in a first state while the control inputs to the second and third transistor switches are in a second state.

Claim 6

The memory cell of claim 3 wherein the means for providing control input comprises: a) a means for applying an electrical signal across the first and second terminals of the memory cell; b) a means for sensing the level of the current flow through the second terminal of the memory cell; and c) a means, responsive to the sensing means, for putting the control inputs to the first and fourth transistor switches in a first state when the sensing means indicates the level of the current flow through the second terminal has a first value and in a second state when the level of the current flow through the second terminal has a second value.

Claim 7

The memory cell of claim 4 wherein the first, second, third and fourth transistor switches conduct current when their control inputs are in the first state and are substantially non-conductive when their control inputs are in the second state.

Claim 8

The memory cell of claim 5 wherein the first value of current flow is substantially zero.

Claim 9

In a non-volatile memory of the type wherein information is read from a memory cell by applying an electrical signal across the cell and measuring the current flow into the cell, an improved method of reading the value in the cell comprising: a) applying the electrical signal to the cell; b) measuring the current flow; and c) in response to a current flow exceeding a predetermined level, substantially instantaneously inverting the polarity of the electrical signal applied to the cell.

Claim 10

In a non-volatile memory of the type wherein information is read from a memory cell by applying an electrical signal across the cell and measuring the current flow into the cell, an improved method of reading the value in the cell comprising: a) applying the electrical signal to the cell; b) measuring the current flow; and c) in response to a current flow exceeding a predetermined level, substantially instantaneously inverting the polarity of the electrical signal applied to the cell.

Claim 11

The method of claim 7 wherein the memory is controlled in part by a clock having a predetermined period and the electrical signal is applied during one period and the polarity of the electrical signal is inverted during the same period.

Claim 12

The method of claim 7 wherein the polarity of the electrical signal is inverted in less than 30 nanoseconds.

Claim 13

A non-volatile memory comprising a plurality of cells connected to a grid of control lines, each cell comprising: a) a ferroelectric capacitor having a first terminal and a second terminal; b) a first transistor switch connecting the first terminal of the ferroelectric capacitor to a first control line, said first transistor switch having a second electrode; c) a second transistor switch connecting the second terminal of the ferroelectric capacitor to a second control line, said second transistor switch having a control electrode; d) a third transistor switch connecting the second terminal of the ferroelectric capacitor to a first control line, said third transistor switch having a control electrode; and e) a fourth transistor switch connecting the first terminal of the ferroelectric capacitor to a second control line, said fourth transistor switch having a control electrode.

Claim 14

A non-volatile memory comprising a plurality of cells connected to a grid of control lines, each cell comprising: a) a ferroelectric capacitor having a first terminal and a second terminal; b) a first transistor switch connecting the first terminal of the ferroelectric capacitor to a first control line, said first transistor switch having a second electrode; c) a second transistor switch connecting the second terminal of the ferroelectric capacitor to a second control line, said second transistor switch having a control electrode; d) a third transistor switch connecting the second terminal of the ferroelectric capacitor to a first control line, said third transistor switch having a control electrode; and e) a fourth transistor switch connecting the first terminal of the ferroelectric capacitor to a second control line, said fourth transistor switch having a control electrode.

Claim 15

The non-volatile memory of claim 10 wherein the control electrode of the first transistor is connected to the control electrode of the second transistor and the control electrode of the third transistor is connected to the control electrode of the fourth transistor.

Claim 16

The non-volatile memory of claim 11 additionally comprising a means for producing a logic signal indicating whether the level of current flowing in the second control line exceeds a predetermined threshold.

Claim 17

The non-volatile memory of claim 12 additionally comprising digital logic means for producing an output in a first state when the means for producing a logic signal indicates a level of current flow exceeding the threshold and for maintaining the output in the first state until-receiving a control signal.

Claim 18

The non-volatile memory of claim 13 additionally comprising control logic means for producing a signal indicating when the memory is to perform a read operation.

Claim 19

The non-volatile memory of claim 14 additionally comprising a means for producing a digital signal having a value equaling the logical AND of the signal produced by the control logic means and the output of the digital logic means.

Claim 20

The non-volatile memory of claim 10 additionally comprising a plurality of voltage source means connected to the control lines for producing a voltage across a selected one of the plurality of cells, wherein the voltage sources are switchable to change the polarity of the voltage across the selected one of the plurality of cells.

Claim 21

The memory cell of claim 1 wherein the means for changing the polarity comprises a plurality of switching transistors.