Patent US6063670A successfully refreshed from Google Patents.
US6063670A
Expired / Lapsed
US
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Gate fabrication processes for split-gate transistors
Assignee: Texas Instruments Inc
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Filing: 1998-04-15
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Granted: 2000-05-16
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Expires: 2018-04-15
Abstract
Abstract A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first gate dielectric (20). The disposable layer (22) comprises a material that may be removed selectively with respect to silicon and the gate dielectric, such as germanium. If desired, a second dielectric layer (24) may be formed over the disposable layer (22). A pattern (26) is then formed exposing areas (14) of the circuit where a thinner gate dielectric is desired. The second dielectric layer (24), if it is present, and the disposable layer (22) are removed from the exposed areas. The pattern (26) is then removed. Following pre-gate cleaning, the second gate dielectric (30) is formed. The remaining portions of the disposable layer (22) may be removed either prior to, during, or after the second gate dielectric formation (30).
Inventors
- 👤 Bo-Yang Lin
- 👤 Douglas T. Grider
- 👤 George Misium
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/09; Y; Y10; Y10S; Y10S438/00; Y10S438/911
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
156 words
A method for fabricating an integrated circuit having multiple gate dielectric thicknesses, comprising the steps of: forming a first gate dielectric layer over a semiconductor body; forming a first disposable layer over said first gate dielectric layer, said first disposable layer comprising a material selectively etchable with respect to said first gate dielectric layer and said semiconductor body; forming a pattern over said first disposable layer, said pattern covering a first region of said disposable layer and exposing a second region of said disposable layer; removing at least a portion of said first disposable layer in said second region using said pattern; removing said pattern while said substrate is not exposed; removing at least a portion of said first gate dielectric layer in said second region; and subsequent to removing said pattern, forming a second gate dielectric layer in said second region, said second gate dielectric layer having a thickness different from said first dielectric layer.
Claim 2
Independent Claim
156 words
A method for fabricating an integrated circuit having multiple gate dielectric thicknesses, comprising the steps of: forming a first gate dielectric layer over a semiconductor body; forming a first disposable layer over said first gate dielectric layer, said first disposable layer comprising a material selectively etchable with respect to said first gate dielectric layer and said semiconductor body; forming a pattern over said first disposable layer, said pattern covering a first region of said disposable layer and exposing a second region of said disposable layer; removing at least a portion of said first disposable layer in said second region using said pattern; removing said pattern while said substrate is not exposed; removing at least a portion of said first gate dielectric layer in said second region; and subsequent to removing said pattern, forming a second gate dielectric layer in said second region, said second gate dielectric layer having a thickness different from said first dielectric layer.
Claim 3
Dependent Claim
12 words
The method of claim 1, wherein said pattern is a resist pattern.
Claim 4
Dependent Claim
26 words
The method of claim 1, wherein said step of forming said first gate dielectric layer comprises the step of thermally growing a layer of silicon dioxide.
Claim 5
Dependent Claim
57 words
The method of claim 1, further comprising the steps of: forming a second disposable layer over said first disposable layer prior to said step of forming a pattern; and removing a portion of said second disposable layer in said second region using said pattern prior to said step of removing a portion of said first disposable layer.
Claim 6
Dependent Claim
13 words
The method of claim 4, wherein said second disposable layer comprises silicon dioxide.
Claim 7
Dependent Claim
12 words
The method of claim 1, wherein said first disposable layer comprises germanium.
Claim 8
Dependent Claim
69 words
The method of claim 1, further comprising the step of removing said first disposable layer from said first region after removing said pattern and prior to forming said second gate dielectric layer, wherein said removing step removes said portion of said first disposable layer selectively with respect to said first gate dielectric layer and said semiconductor body without significantly damaging said first gate dielectric layer or said semiconductor body.
Claim 9
Dependent Claim
62 words
The method of claim 1, further comprising the step of removing said first disposable layer from said first region after said step of forming said second gate dielectric layer, wherein said removing step removes said portion of said first disposable layer selectively with respect to said first and second gate dielectric layers without significantly damaging said first or second gate dielectric layers.
Claim 10
Dependent Claim
26 words
The method of claim 1, wherein said step of forming said second gate dielectric layer comprises the step of thermally growing a layer of silicon dioxide.
Claim 11
Dependent Claim
26 words
The method of claim 1, further comprising the steps of: forming high performance transistors in said second region; and forming peripheral circuitry in said first region.
Claim 12
Independent Claim
142 words
A method for fabricating an integrated circuit having dual gate oxide thicknesses, comprising the steps of: forming a first gate oxide layer over a semiconductor body; forming a first disposable layer over said first gate oxide layer, said first disposable layer comprising a material selectively etchable with respect to said first gate oxide layer and said semiconductor body; forming a resist pattern over said first disposable layer, said resist pattern not covering a first gate oxide area and covering a second gate oxide area; removing at least a portion of said first disposable layer in said first gate oxide area; removing said resist while said substrate is not exposed; removing a portion of said first gate oxide layer in said first gate oxide area; and subsequent to removing said resist, forming a second gate oxide layer in said first gate oxide area.
Claim 13
Independent Claim
142 words
A method for fabricating an integrated circuit having dual gate oxide thicknesses, comprising the steps of: forming a first gate oxide layer over a semiconductor body; forming a first disposable layer over said first gate oxide layer, said first disposable layer comprising a material selectively etchable with respect to said first gate oxide layer and said semiconductor body; forming a resist pattern over said first disposable layer, said resist pattern not covering a first gate oxide area and covering a second gate oxide area; removing at least a portion of said first disposable layer in said first gate oxide area; removing said resist while said substrate is not exposed; removing a portion of said first gate oxide layer in said first gate oxide area; and subsequent to removing said resist, forming a second gate oxide layer in said first gate oxide area.
Claim 14
Dependent Claim
61 words
The method of claim 11, further comprising the steps of: forming a second disposable layer over said first disposable layer prior to said step of forming a resist pattern; and removing a portion of said second disposable layer in said thin gate oxide area using said resist pattern prior to said step of removing a portion of said first disposable layer.
Claim 15
Dependent Claim
13 words
The method of claim 12, wherein said second disposable layer comprises silicon dioxide.
Claim 16
Dependent Claim
12 words
The method of claim 11, wherein said first disposable layer comprises germanium.
Claim 17
Dependent Claim
71 words
The method of claim 11, further comprising the step of removing said first disposable layer from said second gate oxide area after removing said pattern and prior to forming said second gate oxide layer, wherein said removing step removes said portion of said first disposable layer selectively with respect to said first gate oxide layer and said semiconductor body without significantly damaging said first gate oxide layer or said semiconductor body.
Claim 18
Dependent Claim
64 words
The method of claim 11, further comprising the step of removing said first disposable layer from said second gate oxide area after said step of forming said second gate oxide layer, wherein said removing step removes said portion of said first disposable layer selectively with respect to said first and second gate oxide layers without significantly damaging said first or second gate oxide layers.
Claim 19
Dependent Claim
30 words
The method of claim 11, further comprising the steps of: forming high performance transistors in said first gate oxide area; and forming peripheral circuitry in said second gate oxide area.
Claim 20
Dependent Claim
22 words
The method of claim 11, wherein the first disposable layer is removed during said step of forming the second gate oxide layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |