Process of selectively producing refractory metal silicide uniform in thickness regardless of conductivity type of silicon thereunder

Claim 2

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) sputtering a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are about 6 nanometers in thickness; and d) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions, in which said step b) includes the sub-steps of b-1) covering said first silicon portion and said second silicon portion with polysilicon layers, respectively, and b-2) implanting an ion into said polysilicon layers, for converting said polysilicon layers into said amorphous layers; and in which said first temperature in step c) is between 300° centigrade to 500° centigrade.

Claim 3

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) sputtering a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are about 6 nanometers in thickness; and d) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions, in which said amorphous silicon layers are deposited on at least said first silicon portion and said second silicon portion through a chemical vapor deposition; and in which said first temperature in step c) is between 300° centigrade to 500° centigrade.

Claim 4

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) sputtering a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are about 6 nanometers in thickness; and d) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions, in which said amorphous silicon layers are deposited on at least said first silicon portion and said second silicon portion through a chemical vapor deposition; and in which said first temperature in step c) is between 300° centigrade to 500° centigrade.

Claim 5

A process of producing refractory metal disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) depositing a refractory metal layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a refractory metal disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said refractory metal and said amorphous silicon form mixed amorphous silicon/refractory metal boundary layers between said first and second silicon portions and said refractory metal layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions; and d) heating said refractory metal layer to a fourth temperature not lower than said second temperature and said third temperature for producing refractory metal disilicide layers on said first and second silicon portions, in which said refractory metal is titanium, and said first temperature ranges from 300 degrees centigrade to 500 degrees centigrade.

Claim 6

A process of producing refractory metal disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) depositing a refractory metal layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a refractory metal disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said refractory metal and said amorphous silicon form mixed amorphous silicon/refractory metal boundary layers between said first and second silicon portions and said refractory metal layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions; and d) heating said refractory metal layer to a fourth temperature not lower than said second temperature and said third temperature for producing refractory metal disilicide layers on said first and second silicon portions, in which said refractory metal is titanium, and said first temperature ranges from 300 degrees centigrade to 500 degrees centigrade.

Claim 7

A process of producing refractory metal disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) depositing a refractory metal layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a refractory metal disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said refractory metal and said amorphous silicon form mixed amorphous silicon/refractory metal boundary layers between said first and second portions and said refractory metal layer; and d) heating said refractory metal layer to a fourth temperature not lower than said second temperature and said third temperature for producing refractory metal disilicide layers on said first and second silicon portions, further comprising the step of placing said semiconductor structure in a high temperature vacuum ambience for sublimating excess n-type impurity coagulated on a surface of said second silicon portion between said step a) and said step b).

Claim 8

A process of producing refractory metal disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) depositing a refractory metal layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a refractory metal disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said refractory metal and said amorphous silicon form mixed amorphous silicon/refractory metal boundary layers between said first and second portions and said refractory metal layer; and d) heating said refractory metal layer to a fourth temperature not lower than said second temperature and said third temperature for producing refractory metal disilicide layers on said first and second silicon portions, further comprising the step of placing said semiconductor structure in a high temperature vacuum ambience for sublimating excess n-type impurity coagulated on a surface of said second silicon portion between said step a) and said step b).

Claim 9

The process as set forth in claim 4, in which said refractory metal is titanium, and the sublimation of said excess n-type impurity is carried out at 450 degrees centigrade for 10 minutes.

Claim 10

A process of fabricating a semiconductor device on a single crystal silicon substrate, comprising the steps of: preparing a semiconductor structure having an n-type single crystal silicon region of said single crystal silicon substrate, a p-type single crystal silicon region of said single crystal silicon substrate, all n-type polysilicon layer over said single crystal silicon substrate, a p-type polysilicon layer over said single crystal silicon substrate and side walls of silicon oxide provided on side surfaces of said n-type and p-type polysilicon layers; covering an exposed surface of said n-type single crystal silicon region, an exposed surface of said p-type single crystal silicon region, an exposed surface of said n-type polysilicon layer and an exposed surface of said p-type polysilicon layer with amorphous silicon layers; heating said semiconductor structure to a first temperature higher than an ambient temperature and lower than a second temperature and a third temperature, said second temperature being for silicidation of titanium and said third temperature being for crystallization of the amorphous silicon, and wherein said first temperature is between 300° centigrade to 500° centigrade; sputtering a titanium layer on an entire surface at said first temperature so as to contact said amorphous silicon layers and cover said side walls therewith, whereby said titanium layer and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are greater than 5 nanometers in thickness; and converting parts of said titanium layer held in contact with said amorphous silicon into titanium disilicide layers; and removing portions of said titanium layer so as to leave said titanium disilicide layers on said n-type single crystal silicon region, said p-type single crystal silicon region, said n-type polysilicon layer and said p-type polysilicon layer.

Claim 11

A process of fabricating a semiconductor device on a single crystal silicon substrate, comprising the steps of: preparing a semiconductor structure having an n-type single crystal silicon region of said single crystal silicon substrate, a p-type single crystal silicon region of said single crystal silicon substrate, all n-type polysilicon layer over said single crystal silicon substrate, a p-type polysilicon layer over said single crystal silicon substrate and side walls of silicon oxide provided on side surfaces of said n-type and p-type polysilicon layers; covering an exposed surface of said n-type single crystal silicon region, an exposed surface of said p-type single crystal silicon region, an exposed surface of said n-type polysilicon layer and an exposed surface of said p-type polysilicon layer with amorphous silicon layers; heating said semiconductor structure to a first temperature higher than an ambient temperature and lower than a second temperature and a third temperature, said second temperature being for silicidation of titanium and said third temperature being for crystallization of the amorphous silicon, and wherein said first temperature is between 300° centigrade to 500° centigrade; sputtering a titanium layer on an entire surface at said first temperature so as to contact said amorphous silicon layers and cover said side walls therewith, whereby said titanium layer and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are greater than 5 nanometers in thickness; and converting parts of said titanium layer held in contact with said amorphous silicon into titanium disilicide layers; and removing portions of said titanium layer so as to leave said titanium disilicide layers on said n-type single crystal silicon region, said p-type single crystal silicon region, said n-type polysilicon layer and said p-type polysilicon layer.

Claim 12

A process of producing titanium disilicide layers, comprising the steps of: preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; forming amorphous silicon layers on said first silicon portion and said second silicon portion; sputtering a titanium layer on at least said amorphous silicon layers at a first temperature ranges from 300° centigrade to 500° centigrade, such that said first temperature is sufficient to cause a phase C54 titanium disilicide structure to form when said titanium layer is annealed, where said first temperature is lower than a second temperature for producing a titanium disilicide and a third temperature for crystallizing said amorphous silicon layers, whereby said titanium layer and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are greater than 5 nanometers in thickness; and heating said titanium layer to a fourth temperature, not lower than said second temperature and said third temperature, for annealing to produce said phase C54 titanium disilicide layers on said first and second silicon portions.

Claim 13

A process of producing titanium disilicide layers, comprising the steps of: preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; forming amorphous silicon layers on said first silicon portion and said second silicon portion; sputtering a titanium layer on at least said amorphous silicon layers at a first temperature ranges from 300° centigrade to 500° centigrade, such that said first temperature is sufficient to cause a phase C54 titanium disilicide structure to form when said titanium layer is annealed, where said first temperature is lower than a second temperature for producing a titanium disilicide and a third temperature for crystallizing said amorphous silicon layers, whereby said titanium layer and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are greater than 5 nanometers in thickness; and heating said titanium layer to a fourth temperature, not lower than said second temperature and said third temperature, for annealing to produce said phase C54 titanium disilicide layers on said first and second silicon portions.

Claim 14

The process as set forth in claim 7, in which said heating step is performed in a nitrogen atmosphere.

Claim 15

The process as set forth in claim 8, further including the step of removing portions of said titanium layer so as to leave said titanium disilicide layers on said first and second silicon portions.

Claim 16

A process of producing a titanium disilicide layer, comprising the steps of: forming an amorphous silicon layer on a silicon substrate; sputtering a titanium metal layer on at least said doped amorphous silicon, with said silicon substrate temperature at a first temperature which is between 300 degrees centigrade and 500 degrees centigrade, whereby said refractory metal and said amorphous silicon form mixed amorphous silicon/refractory metal boundary layers between said first and second silicon portions and said refractory metal layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions; and heating said titanium metal layer to a temperature higher than said first temperature, sufficient to produce a titanium disilicide, and a second temperature, sufficient for crystallizing said amorphous silicon layer.

Claim 17

A process of producing a titanium disilicide layer, comprising the steps of: forming an amorphous silicon layer on a silicon substrate; sputtering a titanium metal layer on at least said doped amorphous silicon, with said silicon substrate temperature at a first temperature which is between 300 degrees centigrade and 500 degrees centigrade, whereby said refractory metal and said amorphous silicon form mixed amorphous silicon/refractory metal boundary layers between said first and second silicon portions and said refractory metal layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions; and heating said titanium metal layer to a temperature higher than said first temperature, sufficient to produce a titanium disilicide, and a second temperature, sufficient for crystallizing said amorphous silicon layer.

Claim 18

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) sputtering a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature ranging from 300° centigrade to 500° centigrade which is lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions; and d) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions.

Claim 19

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) sputtering a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature ranging from 300° centigrade to 500° centigrade which is lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer, wherein said mixed amorphous silicon/titanium boundary layers trap dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers, and further wherein said mixed amorphous silicon/titanium boundary layers are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions; and d) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions.

Claim 20

The process as set forth in claim 11, in which an ion is implanted into said first silicon portion and said second silicon portion so as to form said amorphous silicon layers.

Claim 21

The process as set forth in claim 11, in which said ion is produced from a substance selected from the group consisting of arsenic and boron difluoride.

Claim 22

The process as set forth in claim 12, in which said ion is formed from arsenic, and arsenic ion is implanted at a dose of 3.0×10 14 cm -2 under an acceleration energy of 30 KeV.

Claim 23

The process as set forth in claim 11, in which said first silicon portion and said second silicon portion are subjected to a reverse sputtering using an inert gas so as to form said amorphous silicon layers.

Claim 24

The process as set forth in claim 15, in which said inert gas is argon.

Claim 25

The process as set forth in claim 11, in which said step b) includes the sub-steps of b-1) covering said first silicon portion and said second silicon portion with polysilicon layers, respectively, and b-2) implanting an ion into said polysilicon layers, for converting said polysilicon layers into said amorphous layers.

Claim 26

The process as set forth in claim 11, in which said titanium layer is covered with a protective layer preventing said titanium layer from a reaction with a substance except for the silicon.

Claim 27

The process as set forth in claim 18, in which said protective layer is formed of titanium nitride.

Claim 28

The process as set forth in claim 18, further comprising the step of removing said protective layer and a residue of said titanium layer after said step d.

Claim 29

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) depositing a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer and wherein said mixed amorphous silicon/titanium boundary layers between said first and second portions and said titanium layer are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions d) trapping said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers between said first and second portions and said titanium layer; and e) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions.

Claim 30

A process of producing titanium disilicide layers, comprising the steps of: a) preparing a semiconductor structure having a first silicon portion doped with a p-type impurity and a second silicon portion doped with an n-type impurity; b) forming amorphous silicon layers on said first silicon portion and said second silicon portion; c) depositing a titanium layer on at least said amorphous silicon layers while maintaining said semiconductor structure at a first temperature above all normal ambient temperatures and lower than a second temperature and a third temperature, said second temperature being for producing a titanium disilicide and said third temperature being for crystallizing said amorphous silicon layers, whereby said titanium and said amorphous silicon form mixed amorphous silicon/titanium boundary layers between said first and second silicon portions and said titanium layer and wherein said mixed amorphous silicon/titanium boundary layers between said first and second portions and said titanium layer are of approximately equal thickness to said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions d) trapping said dopant impurities which are present in said first and second silicon portions in excess of the respective solubility levels of said first and second silicon portions within said mixed amorphous silicon/titanium boundary layers between said first and second portions and said titanium layer; and e) heating said titanium layer to a fourth temperature not lower than said second temperature and said third temperature for producing titanium disilicide layers on said first and second silicon portions.