NMOS field effect transistors and methods of forming NMOS field effect transistors

Claim 2

A semiconductor processing method of forming an NMOS field effect transistor comprising the following steps: forming a patterned gate over a semiconductor substrate; after forming the gate, forming a mesa of semiconductive material beneath the patterned gate, the substrate defining a semiconductive substrate floor and the mesa comprising opposing, substantially vertical wall sections rising upwardly from the floor; and forming a pair of opposing LDD regions within the mesa wall sections and substrate floor, the respective LDD regions having a first portion running along one of the mesa wall sections and a second portion running along the semiconductor substrate floor, the first and second portions of the respective LDD regions being interconnected to form respective elongated and angled LDD regions extending from the mesa into the bulk semiconductor substrate; the step of forming the pair of opposing LDD regions comprising: depositing a layer of phosphosilicate glass over the mesa wall sections and substrate floor, the layer of phosphosilicate glass lying conformally over the mesa wall sections and substrate floor; and subjecting the substrate to conditions effective to out-diffuse phosphorus from the phosphosilicate glass layer into the mesa wall sections and the substrate floor.

Claim 3

The semiconductor processing method of forming an NMOS transistor of claim 1 further comprising forming halo regions within the mesa wall sections.

Claim 4

The semiconductor processing method of forming an NMOS transistor of claim 1 further comprising forming halo regions within the mesa wall sections and within the substrate floor.

Claim 5

A semiconductor processing method of forming an NMOS field effect transistor comprising the following steps: forming a patterned gate over a semiconductor substrate, the gate having opposing sidewalls; etching into the semiconductor substrate to define a mesa of semiconductive material beneath the patterned gate; after the etching, the substrate defining a semiconductive substrate floor and the mesa comprising opposing, substantially vertical wall sections rising upwardly from the floor; forming a pair of opposing halo implants within the mesa wall sections and substrate floor; after forming the pair of opposing halo implants, forming a pair of opposing LDD regions within the semiconductive mesa and overlaying the halo implants, the respective LDD regions having a first portion running along one of the mesa wall sections and a second portion running along the semiconductor substrate floor, the first and second portions of the respective LDD regions being interconnected to form respective elongated and angled LDD regions extending from the mesa into the bulk semiconductor substrate; the step of forming the pair of opposing LDD regions comprising: depositing a layer of phosphosilicate glass over the mesa wall sections and substrate floor, the layer of phosphosilicate glass lying conformally over the mesa wall sections and substrate floor; and subjecting the substrate to conditions effective to out-diffuse phosphorus from the phosphosilicate glass layer into the mesa wall sections and the substrate floor; forming a layer of electrically insulative material over the gate sidewalls and over the mesa wall sections, the layer of insulating material covering the first and the second portions of the LDD regions; and after forming the electrically insulative material over the gate sidewalls and mesa wall sections, doping n-type conductivity enhancing impurity into the bulk substrate floor to form source and drain diffusion regions within the floor which respectively interconnect with the opposing, continuous, elongated, and angled LDD regions extending from the mesa; the electrically insulative layer substantially masking the LDD regions from the source and drain doping.

Claim 6

A semiconductor processing method of forming an NMOS field effect transistor comprising the following steps: forming a patterned gate over a semiconductor substrate, the gate having opposing sidewalls; etching into the semiconductor substrate to define a mesa of semiconductive material beneath the patterned gate; after the etching, the substrate defining a semiconductive substrate floor and the mesa comprising opposing, substantially vertical wall sections rising upwardly from the floor; forming a pair of opposing halo implants within the mesa wall sections and substrate floor; after forming the pair of opposing halo implants, forming a pair of opposing LDD regions within the semiconductive mesa and overlaying the halo implants, the respective LDD regions having a first portion running along one of the mesa wall sections and a second portion running along the semiconductor substrate floor, the first and second portions of the respective LDD regions being interconnected to form respective elongated and angled LDD regions extending from the mesa into the bulk semiconductor substrate; the step of forming the pair of opposing LDD regions comprising: depositing a layer of phosphosilicate glass over the mesa wall sections and substrate floor, the layer of phosphosilicate glass lying conformally over the mesa wall sections and substrate floor; and subjecting the substrate to conditions effective to out-diffuse phosphorus from the phosphosilicate glass layer into the mesa wall sections and the substrate floor; forming a layer of electrically insulative material over the gate sidewalls and over the mesa wall sections, the layer of insulating material covering the first and the second portions of the LDD regions; and after forming the electrically insulative material over the gate sidewalls and mesa wall sections, doping n-type conductivity enhancing impurity into the bulk substrate floor to form source and drain diffusion regions within the floor which respectively interconnect with the opposing, continuous, elongated, and angled LDD regions extending from the mesa; the electrically insulative layer substantially masking the LDD regions from the source and drain doping.