Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions

Claim 2

An integrated circuit having protection against electrostatic discharge, the integrated circuit comprising: a pin through which input signals to or output signals from said integrated circuit are conducted; at least one lightly doped drain (LDD) transistor coupled to said pin for receiving said input signals or producing said output signals; and a non-LDD metaloxide semiconductor (MOS) transistor coupled to said pin for providing said protection against electostatic discharge for said LDD transistor, said non-LDD MOS transistor having a highly-doped source region, a highly-doped drain region and a gate region, both of said highly-doped source and drain regions being separated from said gate region by an undoped region; wherein, in the event of an electrostatic discharge (ESD) event at the pin, a portion of the ESD is dissipated through the non-LDD MOS transistor thereby protecting said LDD transistor.

Claim 3

The integrated circuit of claim 1, wherein said non-LDD MOS transistor further comprises: a substrate of a first conductivity type; a selectively patterned gate oxide formed on said substrate; a gate formed on said gate oxide, said oxide and said gate defining sidewalls on said substrate; a channel region beneath said gate in said substrate; a first highly doped region comprising said source region, having a conductivity of a second type, and formed in said substrate a first predetermined lateral distance from said sidewalls of said gate and adjacent said channel region, said first highly doped region coupled between said channel region and a pin of the integrated circuit; a first undoped region in said substrate separating said first highly-doped region from a point on said substrate adjoined by one of said sidewalls; a second highly doped region comprising said drain region, having a conductivity of said second type, and formed in said substrate a second predetermined lateral distance from said sidewalls of said gate and adjacent said channel region, said second highly doped region coupled between said channel region and a ground line of the integrated circuit; and a second undoped region in said substrate separating said second highly-doped region from a point on said substrate adjoined by a second of said sidewalls; wherein, in the event of an ESD occurrence at the pin, said first highly doped region, said channel region and said second highly doped region form a conductive path to dissipate the ESD.

Claim 4

The integrated circuit of claim 2, wherein said non-LDD transistor further comprises: a parasitic bipolar transistor having an emitter formed in said first highly doped region, a base formed in said channel region, and a collector formed in said second highly doped region, wherein, in the event of an ESD occurrence at the pin, said parasitic bipolar transistor operates to dissipate a portion of the ESD.

Claim 5

The integrated circuit of claim 1, wherein the LDD transistor have a channel width of 1.0 micron or less.

Claim 6

The integrated circuit of claim 1, further comprising a ground line coupled to said non-LDD MOS transistor, wherein in the event of an ESD occurrence at the pin, a portion of the ESD is dissipated through the non-LDD MOS transistor to said ground line.