US6021265A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interoperability with multiple instruction sets
Assignee: ARM Ltd
•
Filing: 1997-04-14
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Granted: 2000-02-01
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Expires: 2017-04-14
Abstract
Abstract Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.
Inventors
- 👤 Edward Colles Nevill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/30181; G06F9/30196; G06F9/32; G06F9/321
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
160 words
Data processing apparatus comprising: (i) a processor core operable to execute successive program instruction words of a predetermined plurality of instruction sets stored in a data memory; (ii) a program counter register for indicating an address of a next program instruction word in said data memory; (iii) logic operable to modify the contents of said program counter register in response to a current program instruction word; (iv) a processor core controller, responsive to one or more predetermined indicator bits of said program counter register, operable to control said processor core to execute program instruction words of a current instruction set selected from said predetermined plurality of instruction sets and specified by the state of said one or more indicator bits of said program counter register; and (v) a memory access controller operable to access program instruction words stored in said data memory, said access controller not being responsive to said one or more indicator bits of said program counter register.
Claim 2
Dependent Claim
160 words
Data processing apparatus comprising: (i) a processor core operable to execute successive program instruction words of a predetermined plurality of instruction sets stored in a data memory; (ii) a program counter register for indicating an address of a next program instruction word in said data memory; (iii) logic operable to modify the contents of said program counter register in response to a current program instruction word; (iv) a processor core controller, responsive to one or more predetermined indicator bits of said program counter register, operable to control said processor core to execute program instruction words of a current instruction set selected from said predetermined plurality of instruction sets and specified by the state of said one or more indicator bits of said program counter register; and (v) a memory access controller operable to access program instruction words stored in said data memory, said access controller not being responsive to said one or more indicator bits of said program counter register.
Claim 3
Dependent Claim
63 words
Apparatus according to claim 1, comprising: a first instruction decoder for decoding program instruction words of a first instruction set; and a second instruction decoder for decoding program instruction words of a second instruction set; and in which said processor core controller is operable to control either said first instruction decoder or said second instruction decoder to decode a current program instruction word.
Claim 4
Dependent Claim
39 words
Apparatus according to claim 2, in which: program instruction words of said first instruction set are X-bit program instruction words; and program instruction words of said second instruction set are Y-bit program instruction words; Y being different to X.
Claim 5
Dependent Claim
39 words
Apparatus according to claim 1, in which: program instruction words of a first instruction set are X-bit program instruction words; and program instruction words of a second instruction set are Y-bit program instruction words; Y being different to X.
Claim 6
Dependent Claim
14 words
Apparatus according to claim 3, in which Y is 16 and X is 32.
Claim 7
Dependent Claim
14 words
Apparatus according to claim 4, in which Y is 16 and X is 32.
Claim 8
Dependent Claim
30 words
Apparatus according to claim 1, in which said one or more indicator bits of said program counter register are one or more most significant bits of said program counter register.
Claim 9
Dependent Claim
30 words
Apparatus according to claim 1, in which said one or more indicator bits of said program counter register are one or more least significant bits of said program counter register.
Claim 10
Dependent Claim
30 words
Apparatus according to claim 2, in which said one or more indicator bits of said program counter register are one or more least significant bits of said program counter register.
Claim 11
Dependent Claim
30 words
Apparatus according to claim 3, in which said one or more indicator bits of said program counter register are one or more least significant bits of said program counter register.
Claim 12
Dependent Claim
30 words
Apparatus according to claim 4, in which said one or more indicator bits of said program counter register are one or more least significant bits of said program counter register.
Claim 13
Dependent Claim
30 words
Apparatus according to claim 5, in which said one or more indicator bits of said program counter register are one or more least significant bits of said program counter register.
Claim 14
Dependent Claim
30 words
Apparatus according to claim 6, in which said one or more indicator bits of said program counter register are one or more least significant bits of said program counter register.
Claim 15
Dependent Claim
17 words
Apparatus according to claim 1, comprising a data memory for storing program instruction words to be executed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-31 | 2003-08-02 | 2004-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-31 | 2007-08-02 | 2008-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-31 | 2011-08-02 | 2012-02-01 | $7700.00 | Window Closed / Lapsed |