EP0306920A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processor having expanded operating functions
Assignee: NEC Corp
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Filing: 1988-09-07
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Granted: —
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Expires: 2008-09-07
Abstract
Abstract A data processor is disclosed which includes a program memory storing a string of instruction, a program counter producing address data for designating a memory location of the program memory storing an instruction to be executed, an instruction decoder decoding the instruction read-out from the program memory and producing a first control signal, and an execution unit executing a first operation in response to the first control signal. The processor further includes a control signal generation circuit detecting that the address data from the program counter takes a specific content and producing a second control signal in response thereto. The processor thus executes a second operation responsive to the second control signal in parallel to the first operation.
Inventors
- 👤 Kazuhiko Ono
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 19:43
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30145; G06F9/32; G06F9/322; G06F9/328
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
122 words
A data processor comprising a program memory storing a string of instructions, an address circuit producing and supplying address data to said program memory to designate a memory location storing an instruction to be executed, decoder means for decoding the instruction read from said program memory and for producing at least one first control signal, means for detecting a specific address data from said address circuit to generate a second control signal independently of said at least one first control signal, and execution means responsive to said at least one first control signal and said second control signal for executing a first operation based upon said at least one first control signal and a second operation based upon said second control signal.
Claim 2
Dependent Claim
122 words
A data processor comprising a program memory storing a string of instructions, an address circuit producing and supplying address data to said program memory to designate a memory location storing an instruction to be executed, decoder means for decoding the instruction read from said program memory and for producing at least one first control signal, means for detecting a specific address data from said address circuit to generate a second control signal independently of said at least one first control signal, and execution means responsive to said at least one first control signal and said second control signal for executing a first operation based upon said at least one first control signal and a second operation based upon said second control signal.
Claim 3
Dependent Claim
68 words
The processor as claimed in claim 1, wherein said decoder means produces a third control signal in response to the instruction read from said program memory by the address data different from said specific address data, and said execution means includes a gate means supplied with said second and third control signal and means responsive to an output of said gate means for performing a predetermined data processing.
Claim 4
Dependent Claim
15 words
The processor as claimed in claim 2, wherein said gate means is an OR gate.
Claim 5
Dependent Claim
130 words
A data processor comprising a program memory storing a plurality of instructions at respective memory locations thereof, a program counter producing address data whose content is changed in a predetermined order, first means responsive to said address data for producing a first control signal when said address data takes a predetermined content and for producing an access signal for making access to one memory location of said program memory, second means for reading out the instruction stored in the memory location which is made access by said access signal and for producing a set of second control signals in response to the read-out instruction, and execution means for executing a first operation responsive to said first control signal and a second operation responsive to said set of second control signals.
Claim 6
Dependent Claim
130 words
A data processor comprising a program memory storing a plurality of instructions at respective memory locations thereof, a program counter producing address data whose content is changed in a predetermined order, first means responsive to said address data for producing a first control signal when said address data takes a predetermined content and for producing an access signal for making access to one memory location of said program memory, second means for reading out the instruction stored in the memory location which is made access by said access signal and for producing a set of second control signals in response to the read-out instruction, and execution means for executing a first operation responsive to said first control signal and a second operation responsive to said set of second control signals.
Claim 7
Dependent Claim
46 words
The data processor as claimed in claim 4, wherein said first means includes a control signal generation circuit detecting that said address data takes said predetermined content to produce said first control signal and an address decoder decoding said address data to produce said access signal.
Claim 8
Dependent Claim
36 words
The data processor as claimed in claim 4, wherein said first means comprises an address decoder decoding said address data to produce said access signal and said access signal is employed as said first control signal.
Claim 9
Dependent Claim
64 words
The data processor as claimed in claim 4, wherein said execution means includes a gate circuit supplied with said first control signal and a part of said set of second control signals so that said execution means executes said first operation when at least one of said first control signal and said part of said set of second control signals takes an active level.
Claim 10
Dependent Claim
104 words
A processor comprising a program counter producing address data, a program memory storing a plurality of instructions for processing, means responsive to said address data for reading out the instruction from said program memory, means for decoding the instruction read from said program memory to produce a first control signal, means responsive to a predetermined content of said address data for producing a second control signal while said decoding means decodes the instruction read from said program memory, and an execution unit performing a first operation responsive to said first control signal in parallel to a second operation responsive to said second control signal.
Claim 11
Dependent Claim
104 words
A processor comprising a program counter producing address data, a program memory storing a plurality of instructions for processing, means responsive to said address data for reading out the instruction from said program memory, means for decoding the instruction read from said program memory to produce a first control signal, means responsive to a predetermined content of said address data for producing a second control signal while said decoding means decodes the instruction read from said program memory, and an execution unit performing a first operation responsive to said first control signal in parallel to a second operation responsive to said second control signal.
References Cited (Backward Citations)
No citation records indexed.
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