EP0324308A2
Expired / Lapsed
EP
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Method and system for decoding plural incompatible format instructions
Assignee: International Business Machines Corp
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Filing: 1988-11-08
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Granted: —
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Expires: 2008-11-08
Abstract
Abstract This invention relates to the architectural design of a data processing system and its method of operation which permits normally incompatible plural format instructions for dissimilar processors to be placed intermixed in the instruction storage of a single machine but to be accurately decoded and executed properly regardless. Instructions in different formats which are normally incompatible, are placed in predefined or segregated areas of the instruction store (2). Instructions are fetched and decoded in an instruction decode memory (5) in a manner which uses portions of both the fetched-from address in the instruction (2) store and the instruction itself. Decoding is thus determined in part by where in the instruction store the instruction resided when fetched, and by the specific instruction itself. This approach is compatible with both ordinary processor architecture and with pipelined processor architectures.
Inventors
- 👤 Larry Donald Larsen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 20:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/30185; G06F9/30196
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
103 words
A method of decoding properly for execution normally incompatible plural format instructions into compatible single format execution codes in a processor, characterized by the steps of: fetching sequentially for decoding and execution said instructions from a first addressable storage means; and decoding sequentially said fetched instructions for execution in said processor by accessing execution codes stored in a second addressable storage means by utilizing at least a portion of the address in said first addressable storage from which each said instruction was fetched together with at least a portion of said fetched instruction itself as the address for said second addressable storage means.
Claim 2
Independent Claim
103 words
A method of decoding properly for execution normally incompatible plural format instructions into compatible single format execution codes in a processor, characterized by the steps of: fetching sequentially for decoding and execution said instructions from a first addressable storage means; and decoding sequentially said fetched instructions for execution in said processor by accessing execution codes stored in a second addressable storage means by utilizing at least a portion of the address in said first addressable storage from which each said instruction was fetched together with at least a portion of said fetched instruction itself as the address for said second addressable storage means.
Claim 3
Dependent Claim
29 words
The method as described in Claim 1, further comprising the step of segregating by format said instructions into separately identifiable groups of locations in said first addressable storage means.
Claim 4
Dependent Claim
29 words
The method as described in Claim 1, further comprising the step of retaining sequentially the addresses in said first addressable storage means from which said process instructions are fetched.
Claim 5
Dependent Claim
69 words
The method as described in Claim 1 to 3, further comprising the step of arranging for access the execution codes for each said instruction in said second addressable storage means, said arranging being done at locations therein that are determined by at least a portion of each said instruction together with at least a portion of the address in said first addressable storage means wherein said process instruction resides.
Claim 6
Dependent Claim
108 words
A data processing system having plural and compatible format instruction and decoding execution capability, characterized in that it comprises: a first addressable storage means acting as an instruction store, said instruction store containing instructions in two or more incompatible formats for execution in said data processing system, and a second addressable storage means acting as an execution code store, the contents of said execution code store being arranged to be addressed for each said instruction in said instruction store by an address utilizing at least a portion of said instruction together with at least a portion of the address in said instruction store at which said instruction resides.
Claim 7
Dependent Claim
108 words
A data processing system having plural and compatible format instruction and decoding execution capability, characterized in that it comprises: a first addressable storage means acting as an instruction store, said instruction store containing instructions in two or more incompatible formats for execution in said data processing system, and a second addressable storage means acting as an execution code store, the contents of said execution code store being arranged to be addressed for each said instruction in said instruction store by an address utilizing at least a portion of said instruction together with at least a portion of the address in said instruction store at which said instruction resides.
Claim 8
Dependent Claim
27 words
System as described in Claims 5 further comprising means for retrieving sequentially the addresses in said first addressable storage means from which said process instructions are fetched.
References Cited (Backward Citations)
No citation records indexed.
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