Microprocessor compatible with any software represented by different types of instruction formats

Claim 2

A microprocessor including a central processing unit capable of executing only instructions of a first type having a first bit length but incapable of executing instructions of a second type having a second bit length different from said first bit length which is different from said type, said central processing unit having an instruction decoder for decoding only the instructions of the first type, said microprocessor further comprising: receiving means for receiving an instruction of one of said first and second types which is indicative of a predetermined operation; means for directly transferring the instruction indicative of said predetermined operation received by said receiving means only when said received instruction is of said first type; conversion memory means provided outside said central processing unit for converting the received instruction of said second type indicative of said predetermined operation into an instruction of said first type indicative of said predetermined operation, said conversion memory means including storing means for storing instructions of said first type and applying means for applying at least a part of said instruction of said second type received by said receiving means to said storing means as an address for said storing means to thereby read out of said storing means at least one instruction of said first type indicative of said predetermined function; and means provided outside said central processing unit for transferring the read-out instruction of said first type to said instruction decoder when the instruction received by said receiving means is of said second type, whereby the instruction of said second type indicative of a predetermined operation is converted to an instruction of said first type indicative of said predetermined operation through said conversion memory means and said central processing unit thereafter performs said predetermined operation.

Claim 3

(Amended) A microprocessor as claimed in claim 11, in which said applying means includes means for generating an address portion for designating a further first type instruction to be read out of said storing means subsequent to said at least one instruction.

Claim 4

(Amended) A microprocessor as claimed in claim 2, in which said generating means generates said address portion according to a content of said at least one first type instruction.

Claim 5

(Amended) A microprocessor as claimed in 11, in which said applying means applies two addresses to said storing means when the at least one first type instruction corresponding to the received second type instruction consists of two bytes.

Claim 6

(Amended) A microprocessor as claimed in claim 11, in which said storing means stores a specific information indicating that the received second type instruction consists of a plurality of bytes.

Claim 7

(Amended) A microprocessor as claimed in claim 5, in which said specific information is read out of said storing means according to a first byte of the received second type instruction.

Claim 8

A microprocessor comprising a central processing unit which can execute instructions of a first bit length but cannot execute instructions of a second bit length different from said first bit length, said central processing unit including an instructions decoder for decoding the instructions of said first bit length, said instruction decoder being unable to decode the instruction of said second bit length, means for receiving an instruction of one of said first bit length and said second bit length which is indicative of a predetermined operation, means for directly transferring the instruction received by said receiving means to said instruction decoder only when said received instruction is of said first bit length, a conversion memory provided outside said central processing unit and having an input port and an output port and storing instructions of said first bit length, means for operatively applying at least part of the instruction of said second bit length received by said receiving means to the input port of said conversion memory to thereby produce at the output port of said conversion memory the instruction of said first bit length indicative of said predetermined operation, and means for transferring the instruction of said first bit length produced at the output port of said conversion memory to said instruction decoder only when the instruction received by said receiving means is of said second bit length.

Claim 9

A microprocessor comprising a central processing unit which can execute instructions of a first bit length but cannot execute instructions of a second bit length different from said first bit length, said central processing unit including an instructions decoder for decoding the instructions of said first bit length, said instruction decoder being unable to decode the instruction of said second bit length, means for receiving an instruction of one of said first bit length and said second bit length which is indicative of a predetermined operation, means for directly transferring the instruction received by said receiving means to said instruction decoder only when said received instruction is of said first bit length, a conversion memory provided outside said central processing unit and having an input port and an output port and storing instructions of said first bit length, means for operatively applying at least part of the instruction of said second bit length received by said receiving means to the input port of said conversion memory to thereby produce at the output port of said conversion memory the instruction of said first bit length indicative of said predetermined operation, and means for transferring the instruction of said first bit length produced at the output port of said conversion memory to said instruction decoder only when the instruction received by said receiving means is of said second bit length.

Claim 10

A microprocessor as claimed in claim 7, in which said first bit length is longer than said second bit length.

Claim 11

A microprocessor comprising: a central processing unit having an instruction decoder generating at least one control signal by decoding an instruction of a first type, said instruction decoder being unable to decode an instruction of a second type different from said first type, and an execution means executing a program according to the control signal generated from said instruction decoder, a data bus receiving an instruction of one of said first and second types from the outside of said microprocessor, a conversion memory provided outside said central processing unit and having an input port and an output port, said conversion memory storing instructions of said first type and producing one of the instructions stored therein at its output port in accordance with a state of the input port thereof, address control means coupled to said data bus and the input port of said conversion memory, a selector having a first input port coupled to said data bus and a second input port coupled to said output port of said conversion memory and having an output port, said selector operatively transferring data at the first input port thereof to its output port without changing data at said first input port in a first mode and transferring data at its second input port to its output port in a second mode, a control circuit coupled to said selector for setting said selector in said first mode when the instruction received at said data bus is of said first type and in said second mode when the instruction received at said data bus is of said second type, and means for applying information at the output port of said selector to said instruction decoder, whereby the instruction of said second type indicative of a predetermined operation is converted into the instruction of said first type indicative of said predetermined operation through said conversion memory and the converted instruction of said first type is applied to said instruction decoder.

Claim 12

A microprocessor comprising: a central processing unit having an instruction decoder generating at least one control signal by decoding an instruction of a first type, said instruction decoder being unable to decode an instruction of a second type different from said first type, and an execution means executing a program according to the control signal generated from said instruction decoder, a data bus receiving an instruction of one of said first and second types from the outside of said microprocessor, a conversion memory provided outside said central processing unit and having an input port and an output port, said conversion memory storing instructions of said first type and producing one of the instructions stored therein at its output port in accordance with a state of the input port thereof, address control means coupled to said data bus and the input port of said conversion memory, a selector having a first input port coupled to said data bus and a second input port coupled to said output port of said conversion memory and having an output port, said selector operatively transferring data at the first input port thereof to its output port without changing data at said first input port in a first mode and transferring data at its second input port to its output port in a second mode, a control circuit coupled to said selector for setting said selector in said first mode when the instruction received at said data bus is of said first type and in said second mode when the instruction received at said data bus is of said second type, and means for applying information at the output port of said selector to said instruction decoder, whereby the instruction of said second type indicative of a predetermined operation is converted into the instruction of said first type indicative of said predetermined operation through said conversion memory and the converted instruction of said first type is applied to said instruction decoder.

Claim 13

A microprocessor as claimed in claim 9, in which the instruction of said first type is composed of a first bit-length data and the instruction of said second type is composed of a second bit-length data shorter than said first bit-length.