EP0169565A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprocessor compatible with any software represented by different types of instruction formats
Assignee: NEC Corp
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Filing: 1985-07-25
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Granted: —
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Expires: 2005-07-25
Abstract
Abstract A microprocessor include a central processing unit which executes a program according to at least one control signal generated by an instruction decoder. The instruction decoder is designed such that a first type insruction adaptable for the central processing unit can be decoded. A second type instruction unadaptable for the central processing unit is applied as an address to a conversion memory in which the first type instruction corresponding to the second type instruction in their functions is preliminarily stored. The first type instruction in the conversion memory is applied to the instruction decoder instead of the second type instruction. Thus, the second type instruction can be executed by the central processing unit unadaptable for the second type instruction.
Inventors
- 👤 Shigetatsu Katori
- 👤 Yukio Maehashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 19:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/30189
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
114 words
A microprocessor including a central processing unit adaptable for instructions of a first type and an instruction decoder for decoding the instructions of the first type comprising: means for receiving an instruction of a second type unadaptable for said central processing unit; memory means for preliminarily storing instructions of the first type, one of which corresponds to the received second type instruction in an operating function; means for applying said second type instruction as at least one part of an address to said memory means; means for reading the first type instruction out of said memory means according to the address; and means for transferring the read-out first type instruction to said instruction decoder.
Claim 2
Dependent Claim
114 words
A microprocessor including a central processing unit adaptable for instructions of a first type and an instruction decoder for decoding the instructions of the first type comprising: means for receiving an instruction of a second type unadaptable for said central processing unit; memory means for preliminarily storing instructions of the first type, one of which corresponds to the received second type instruction in an operating function; means for applying said second type instruction as at least one part of an address to said memory means; means for reading the first type instruction out of said memory means according to the address; and means for transferring the read-out first type instruction to said instruction decoder.
Claim 3
Dependent Claim
32 words
A microprocessor as claimed in claim 1, in which said applying means includes means for generating an address by which a first type instruction subsequent to said read-out instruction is successively designated.
Claim 4
Dependent Claim
25 words
A microprocessor as claimed in claim 2, in which said generating means generates said address according to a content of said read-out first type instruction.
Claim 5
Dependent Claim
35 words
A microprocessor as claimed in claim 1, in which said applying means applies two addresses to said memory means when the first type instruction corresponding to the received second type instruction consists of two bytes.
Claim 6
Dependent Claim
29 words
A microprocessor as claimed in claim 1, in which said memory means stores a specific information indicating that the received second type instruction consists of a plurality of bytes.
Claim 7
Dependent Claim
30 words
A microprocessor as claimed in claim 5, in which said specific information is read out of said memory means according to a first byte of the received second type instruction.
Claim 8
Dependent Claim
24 words
A microprocessor as claimed in claim 1, further comprising means for coupling said instruction decoder to either said receiving means or said memory means.
Claim 9
Dependent Claim
121 words
A microprocessor comprising an instruction decoder generating at least one control signal by decoding an instruction, an execution means executing a program according to the control signal generated from said instruction decoder, first means for receiving an instruction from the outside of said microprocessor, second means for applying the received instruction to said instruction decoder as it is, third means for inhibiting an application of said received instruction to said instruction decoder, fourth means for storing at least one instruction whose format is different from that of the received instruction, fifth means for generating an address accessing said fourth means according to the received instruction, and sixth means for transferring the instruction accessed by said fifth means to said instruction decoder.
Claim 10
Dependent Claim
121 words
A microprocessor comprising an instruction decoder generating at least one control signal by decoding an instruction, an execution means executing a program according to the control signal generated from said instruction decoder, first means for receiving an instruction from the outside of said microprocessor, second means for applying the received instruction to said instruction decoder as it is, third means for inhibiting an application of said received instruction to said instruction decoder, fourth means for storing at least one instruction whose format is different from that of the received instruction, fifth means for generating an address accessing said fourth means according to the received instruction, and sixth means for transferring the instruction accessed by said fifth means to said instruction decoder.
Claim 11
Dependent Claim
39 words
A microprocessor as claimed in claim 8, in which the received instruction applied to said fifth means for generating the address of said fourth means is the instruction by which a correct execution of said execution means is disturbed.
Claim 12
Dependent Claim
28 words
A microprocessor as claimed in claim 8, in which said instruction decoder, said execution means and said first to sixth means are integrated on a single semiconductor chip.
References Cited (Backward Citations)
No citation records indexed.
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