Method and apparatus for displaying images when an analog-to-digital converter in a digital display unit is unable to sample an analog display signal at a desired high sampling frequency

Claim 3

The method of claim 1, further comprising the steps: (f) sampling each of said plurality of frames encoded in said analog display signal at said optimal sampling frequency if said optimal sampling frequency is not greater than the maximum sampling frequency of an analog to digital converter (ADC) included in said digital display unit; and (g) displaying said images according to the sampled values generated in step (f).

Claim 4

The method of claim 1, wherein step (c) comprises the step of sampling each of said plurality of frames using interleaved sampling.

Claim 5

The method of claim 3, wherein step (c) comprises the further step of sampling each said plurality of frames using 2:1 interleaved sampling.

Claim 6

The method of claim 4, wherein step (d) comprises the step of interpolating said plurality of pixels to generate twice the number of pixels contained in said plurality of pixels.

Claim 7

The method of claim 1, wherein step (c) comprises the step of determining said optimal sampling frequency by multiplying the number of frames received in each second, the number of horizontal lines in each of said plurality of frames and a desired number of samples per each horizontal line.

Claim 8

The method of claim 1, wherein step (d) comprises the step of upscaling said smaller image to fit a size of a digital display screen.

Claim 9

A display circuit for use in a digital display unit of a computer system, said display unit including an analog to digital converter (ADC) for sampling an analog display signal received from a graphics source, an optimal sampling frequency being associated with said analog display signal, said display circuit for generating display signals for a digital display screen, said display circuit comprising: a clock generator circuit for generating a clock signal; a controller for determining whether said optimal sampling frequency is greater than a maximum sampling frequency of said ADC; a pixel qualifier circuit coupled to said controller and said clock generator circuit, said pixel qualifier circuit receiving said clock signal and generating a sampling clock having a frequency lesser than the maximum sampling frequency if said optimal sampling frequency is greater than a maximum sampling frequency of said ADC, wherein said sampling clock having a frequency lesser than the maximum sampling frequency is used by said ADC to sample said analog display signals to generate a plurality of sampled pixel data elements; and an upscaler for upscaling a smaller image represented by said plurality of sampled pixel data elements to generate an upscaled image, wherein said upscaler generates additional pixel data elements based on said sampled pixel data elements to generate said upscaled image, wherein said upscaled image is displayed on a digital display screen.

Claim 10

A display circuit for use in a digital display unit of a computer system, said display unit including an analog to digital converter (ADC) for sampling an analog display signal received from a graphics source, an optimal sampling frequency being associated with said analog display signal, said display circuit for generating display signals for a digital display screen, said display circuit comprising: a clock generator circuit for generating a clock signal; a controller for determining whether said optimal sampling frequency is greater than a maximum sampling frequency of said ADC; a pixel qualifier circuit coupled to said controller and said clock generator circuit, said pixel qualifier circuit receiving said clock signal and generating a sampling clock having a frequency lesser than the maximum sampling frequency if said optimal sampling frequency is greater than a maximum sampling frequency of said ADC, wherein said sampling clock having a frequency lesser than the maximum sampling frequency is used by said ADC to sample said analog display signals to generate a plurality of sampled pixel data elements; and an upscaler for upscaling a smaller image represented by said plurality of sampled pixel data elements to generate an upscaled image, wherein said upscaler generates additional pixel data elements based on said sampled pixel data elements to generate said upscaled image, wherein said upscaled image is displayed on a digital display screen.

Claim 11

The display circuit of claim 8, wherein said clock signal generated by said clock generator circuit has a frequency equal to said optimal sampling frequency.

Claim 12

The display circuit of claim 9, wherein said ADC is coupled to said clock generator circuit to receive said clock signal with said optimal sampling frequency if said optimal sampling frequency is not greater than a maximum sampling frequency of said ADC, where forth said ADC samples said analog display signal at said optimal sampling frequency.

Claim 13

The display circuit of claim 9, wherein said pixel qualifier circuit generates said clock signal with a frequency of half of said optimal sampling frequency such that said ADC performs 2:1 interleaved sampling.

Claim 14

The display circuit of claim 11, further comprising an interpolator for interpolating said plurality of pixels to generate twice the number of pixels contained in said plurality of pixel data elements.

Claim 15

The display circuit of claim 11, wherein said analog display signal comprises a plurality frames including even frames and odd frames, each of said plurality of frames comprising a plurality of horizontal lines including even lines and odd lines, and wherein said pixel qualifier circuit comprises: a frame counting circuit for generating a first logical value when one of said even frames is received and a second logical value when one of said odd frames is received; a line counting circuit for generating a first logical value when one of said even lines is received and a second logical value when one of said odd lines is received; an XOR gate coupled to receive the values generated by said line counting circuit and said frame counting circuit, wherein the output of said XOR gate indicates whether a first half or a second half of a plurality of optimal positions are to be sampled for 2:1 interleaved sampling, wherein said plurality of optimal positions correspond to positions which would be sampled if said analog display signal were sampled at an optimal sampling frequency.

Claim 16

A digital display unit for use in a computer system, said digital display unit for displaying a plurality of images encoded in an analog display signal received from a graphics source, said analog display signal having an associated optimal sampling frequency said digital display unit comprising: an analog to digital converter (ADC) for receiving said analog display signal and a sampling clock, said ADC generating a plurality of sampled pixel data elements by sampling said analog display signal at a sampling frequency of said sampling clock; a clock generator circuit for generating a clock signal; a controller circuit for determining whether said optimal sampling frequency is greater than a maximum sampling frequency of said ADC; a pixel qualifier circuit coupled to said controller and said clock generator circuit, said pixel qualifier circuit receiving said clock signal and generating said sampling clock having a frequency lesser than the maximum sampling frequency if said optimal sampling frequency is greater than a maximum sampling frequency of said ADC, wherein said sampling clock having a frequency lesser than the maximum sampling frequency is used by said ADC to sample said analog display signals to generate a plurality of sampled pixel data elements; and an upscaler for upscaling a smaller image represented by said plurality of sampled pixel data elements to generate an upscaled image, wherein said upscaler generates additional pixel data elements based on said sampled pixel data elements to generate said upscaled image; a digital display screen for displaying said upscaled image; and a panel interface coupled to said upscaler for receiving pixel data elements representative of said upscaled image and generating display signals to display said upscaled image on said digital display screen.

Claim 17

A digital display unit for use in a computer system, said digital display unit for displaying a plurality of images encoded in an analog display signal received from a graphics source, said analog display signal having an associated optimal sampling frequency said digital display unit comprising: an analog to digital converter (ADC) for receiving said analog display signal and a sampling clock, said ADC generating a plurality of sampled pixel data elements by sampling said analog display signal at a sampling frequency of said sampling clock; a clock generator circuit for generating a clock signal; a controller circuit for determining whether said optimal sampling frequency is greater than a maximum sampling frequency of said ADC; a pixel qualifier circuit coupled to said controller and said clock generator circuit, said pixel qualifier circuit receiving said clock signal and generating said sampling clock having a frequency lesser than the maximum sampling frequency if said optimal sampling frequency is greater than a maximum sampling frequency of said ADC, wherein said sampling clock having a frequency lesser than the maximum sampling frequency is used by said ADC to sample said analog display signals to generate a plurality of sampled pixel data elements; and an upscaler for upscaling a smaller image represented by said plurality of sampled pixel data elements to generate an upscaled image, wherein said upscaler generates additional pixel data elements based on said sampled pixel data elements to generate said upscaled image; a digital display screen for displaying said upscaled image; and a panel interface coupled to said upscaler for receiving pixel data elements representative of said upscaled image and generating display signals to display said upscaled image on said digital display screen.

Claim 18

The digital display unit of claim 14, wherein said clock signal generated by said clock generator circuit has a frequency equal to said optimal sampling frequency.

Claim 19

The digital display unit of claim 15, wherein said ADC is coupled to said clock generator circuit to receive said clock signal with said optimal sampling frequency if said optimal sampling frequency is not greater than a maximum sampling frequency of said ADC, where forth said ADC samples said analog display signal at said optimal sampling frequency.

Claim 20

The digital display unit of claim 15, wherein said pixel qualifier circuit generates said clock signal with a frequency of half of said optimal sampling frequency such that said ADC performs 2:1 interleaved sampling.

Claim 21

The digital display unit of claim 17, further comprising an interpolator for interpolating said plurality of pixels to generate twice the number of pixels contained in said plurality of pixel data elements.

Claim 22

A computer system for displaying each of a plurality of images on a digital display unit, each of said plurality of images being encoded in one of a plurality of frames of an analog display signal, said analog display signal having an associated optimal sampling frequency for sampling said analog display signal, said method comprising the steps of: means for receiving said analog display signal in a digital display unit comprised in said computer system; means for determining whether said optimal sampling frequency is greater than the maximum sampling frequency of an analog to digital converter (ADC) included in said digital display unit; means for sampling each of said plurality of frames encoded in said analog display signal at a lower sampling frequency than said optimal sampling frequency to generate a plurality of sampled pixel data elements if said optimal sampling frequency is greater than the maximum sampling frequency of an analog to digital converter (ADC) included in said digital display unit; means for upsealing a smaller image represented by said plurality of sampled pixel data elements to generate an upscaled image, wherein said means for upscaling generates additional pixel data elements based on said sampled pixel data elements to generate said upscaled image; and means for displaying said upscaled image on a digital display screen.

Claim 23

A computer system for displaying each of a plurality of images on a digital display unit, each of said plurality of images being encoded in one of a plurality of frames of an analog display signal, said analog display signal having an associated optimal sampling frequency for sampling said analog display signal, said method comprising the steps of: means for receiving said analog display signal in a digital display unit comprised in said computer system; means for determining whether said optimal sampling frequency is greater than the maximum sampling frequency of an analog to digital converter (ADC) included in said digital display unit; means for sampling each of said plurality of frames encoded in said analog display signal at a lower sampling frequency than said optimal sampling frequency to generate a plurality of sampled pixel data elements if said optimal sampling frequency is greater than the maximum sampling frequency of an analog to digital converter (ADC) included in said digital display unit; means for upsealing a smaller image represented by said plurality of sampled pixel data elements to generate an upscaled image, wherein said means for upscaling generates additional pixel data elements based on said sampled pixel data elements to generate said upscaled image; and means for displaying said upscaled image on a digital display screen.