US5450085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for high speed analog to digital conversion using multiplexed flash sections
Assignee: Samsung Electronics Co Ltd
•
Filing: 1993-10-21
•
Granted: 1995-09-12
•
Expires: 2013-10-21
Abstract
Abstract Analog to digital conversion of signals at rates higher than can be accomplished by a monolithic flash analog to digital converter is achieved using multiple flash analog to digital converters operated in a parallel architecture. Sample timing of the multiple converters is skewed by selecting subfrequencies of a control clock or different phases of a control clock as the source for the sample control signal. The multiple flash converter outputs are then digitally recombined to produce a single output identical to a flash converter operating at a higher speed than could be obtained for a given set of circuit parameters.
Inventors
- 👤 Brett Stewart
- 👤 Miki Moyal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:43
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/02; H03M1/12; H03M1/1205; H03M1/121; H03M1/1215; H03M1/14; H03M1/145; H03M1/34; H03M1/36; H03M1/361; H03M1/362; H03M1/365; H03M1/66; H03M1/74; H03M1/76; H03M1/765
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
141 words
A converter circuit comprising: a plurality of N banks of comparators; an analog input channel for receiving an analog signal and routing said analog signal to first inputs of said comparators; a plurality of voltage references, a different one of each of said plurality of voltage references being routed to a second input of ones of said comparators in each of said comparator banks; and a comparator bank activation circuit for generating a control clock having a pulse rate equal to N times the pulse rate of a system clock, N control clock pulses of the control clock signalling said comparator banks to output one cycle of signals, each of said signals representing an amplitude of said analog signal, wherein in said one cycle each bank of comparators receives a corresponding control clock pulse at selected times within said one cycle.
Claim 2
Dependent Claim
141 words
A converter circuit comprising: a plurality of N banks of comparators; an analog input channel for receiving an analog signal and routing said analog signal to first inputs of said comparators; a plurality of voltage references, a different one of each of said plurality of voltage references being routed to a second input of ones of said comparators in each of said comparator banks; and a comparator bank activation circuit for generating a control clock having a pulse rate equal to N times the pulse rate of a system clock, N control clock pulses of the control clock signalling said comparator banks to output one cycle of signals, each of said signals representing an amplitude of said analog signal, wherein in said one cycle each bank of comparators receives a corresponding control clock pulse at selected times within said one cycle.
Claim 3
Dependent Claim
18 words
The apparatus recited in claim 1, further comprising a voltage divider network forming said plurality of voltage references.
Claim 4
Dependent Claim
18 words
The apparatus recited in claim 1, wherein said analog input channel further comprises a sample and hold circuit.
Claim 5
Dependent Claim
48 words
The apparatus recited in claim 1, wherein said analog input channel further comprises a sample and hold circuit for each comparator bank, each said sample and hold circuit routing samples of said analog signal signals to said first inputs of said comparators in one of said comparator banks.
Claim 6
Dependent Claim
28 words
The apparatus recited in claim 4, wherein said comparator bank activation circuit triggers each said sample and hold circuit to sample said analog signal at said selected times.
Claim 7
Dependent Claim
27 words
The apparatus recited in claim 1, wherein said comparator bank activation circuit includes circuitry for activating said comparator banks at times when said voltage references are stable.
Claim 8
Dependent Claim
17 words
The apparatus recited in claim 1, wherein said converter circuit comprises a flash analog to digital converter.
Claim 9
Dependent Claim
18 words
The apparatus recited in claim 7, wherein said converter circuit is a multi-stage flash analog to digital converter.
Claim 10
Dependent Claim
49 words
The apparatus recited in claim 8, wherein said comparator bank activation circuit comprises circuitry to activate said comparator banks during time periods when said voltage references on said second inputs of said comparators as a result of switching between stages has essentially no effect on outputs of said comparators.
Claim 11
Dependent Claim
18 words
The apparatus recited in claim 7, wherein said converter circuit is a multi-channel flash analog to digital converter.
Claim 12
Dependent Claim
19 words
The apparatus recited in claim 10, wherein said converter circuit further comprises a multi-stage flash analog to digital converter.
Claim 13
Dependent Claim
26 words
The apparatus recited in claim 1, wherein said comparator bank activation circuit activates different comparator banks at a rate determined by subfrequencies of a control clock.
Claim 14
Dependent Claim
37 words
The apparatus recited in claim 12, wherein said rate determined by said subfrequencies equals a rate of said control clock divided by a number equal to a number of comparator banks in said plurality of comparator banks.
Claim 15
Dependent Claim
25 words
The apparatus recited in claim 1, wherein each of said plurality of comparator banks provides a digital output during one cycle of a system clock.
Claim 16
Dependent Claim
74 words
The apparatus recited in claim 1, further comprising: a plurality of switches, each of said switches being connected between one of said second inputs of said comparators and an analog output, said analog output providing an analog representation of digital inputs; and a timing controller controlling each of said switches to connect one of said second inputs of said comparators to said analog output in response to a logic condition of said digital inputs.
Claim 17
Independent Claim
118 words
A method of converting signals, the method comprising the steps of: receiving an analog signal in an analog input channel and routing said analog signal to first inputs of a plurality of comparators arranged in a plurality of N banks of said comparators; routing a plurality of voltage references to said comparators, a different one of each of said plurality of voltage references being routed to a second input of ones of said comparators in each of said comparator banks; generating a control clock having a pulse rate equal to N times a system clock; and signalling said comparator banks to output signals representing an amplitude of said analog signal with said control clock pulses at selected times.
Claim 18
Independent Claim
118 words
A method of converting signals, the method comprising the steps of: receiving an analog signal in an analog input channel and routing said analog signal to first inputs of a plurality of comparators arranged in a plurality of N banks of said comparators; routing a plurality of voltage references to said comparators, a different one of each of said plurality of voltage references being routed to a second input of ones of said comparators in each of said comparator banks; generating a control clock having a pulse rate equal to N times a system clock; and signalling said comparator banks to output signals representing an amplitude of said analog signal with said control clock pulses at selected times.
Claim 19
Dependent Claim
19 words
The method recited in claim 16, further comprising sampling and holding said analog signal in said analog input channel.
Claim 20
Dependent Claim
52 words
The method recited in claim 16, wherein said analog input channel further comprises a sample and hold circuit for each comparator bank, the method further comprising routing samples of said analog signals to said first inputs of said comparators in each of said comparator banks from a corresponding sample and hold circuit.
Claim 21
Dependent Claim
23 words
The method recited in claim 18, wherein each said sample and hold circuit is triggered to sample said analog signal at selected times.
Claim 22
Dependent Claim
20 words
The method recited in claim 16, wherein said comparator banks are activated at times when said voltage references are stable.
Claim 23
Dependent Claim
15 words
The method recited in claim 16, wherein a flash analog to digital conversion is performed.
Claim 24
Dependent Claim
16 words
The method recited in claim 21, wherein a multi-stage flash analog to digital conversion is performed.
Claim 25
Dependent Claim
44 words
The method recited in claim 22, wherein said comparator banks are activated during time periods when disturbances in said voltage references on said second inputs of said comparators as a result of switching between stages has essentially no effect on outputs of said comparators.
Claim 26
Dependent Claim
16 words
The apparatus recited in claim 21, wherein a multi-channel flash analog to digital conversion is performed.
Claim 27
Dependent Claim
16 words
The apparatus recited in claim 24, wherein a multi-stage flash analog to digital conversion is performed.
Claim 28
Dependent Claim
23 words
The method recited in claim 16, wherein said different comparator banks are activated at a rate determined by subfrequencies of a control clock.
Claim 29
Dependent Claim
38 words
The method recited in claim 26, wherein said control clock is at a rate equal to a multiple of a system clock, said multiple being equal to a number of comparator banks in said plurality of comparator banks.
Claim 30
Dependent Claim
27 words
The method recited in claim 27, wherein said rate determined by said subfrequencies equals a rate of said control clock divided by said number of comparator banks.
Claim 31
Dependent Claim
25 words
The apparatus recited in claim 16, wherein each of said plurality of comparator banks provides a digital output during one cycle of a system clock.
Claim 32
Dependent Claim
76 words
The method recited in claim 16, further comprising: providing digital inputs to a plurality of switches, each of said switches being connected between one of said second inputs of said comparators and an analog output, said analog output providing an analog representation of said digital inputs; and controlling each of said switches to connect one of said second inputs of said comparators to said analog output in response to a logic condition of said digital inputs.
References Cited (Backward Citations)
US3597761A
Cited
US4232302A
Cited
US4386339A
Cited
US4456904A
Cited
US4633226A
Cited
GB2190258A
Cited
US4849759A
Cited
US4719447A
Cited
US4973976A
Cited
US4968988A
Cited
US5151700A
Cited
US5093664A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-11 | 1999-03-13 | 1999-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-11 | 2003-03-13 | 2003-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-11 | 2007-03-13 | 2007-09-12 | $7700.00 | Window Closed / Lapsed |