US4994806A
Expired / Lapsed
US
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Flash-successive approximation analog-to-digital converter
Assignee: Samsung Electronics Co Ltd
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Filing: 1989-10-10
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Granted: 1991-02-19
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Expires: 2009-10-10
Abstract
Abstract This invention relates to a flash-successive approximation analog-to-digital converter combining the low speed, high resolution successive approximation method of conversion with the high speed, low resolution flash method of conversion, which provides the advantages of higher conversion speed with no increased conversion error.
Inventors
- 👤 Lee Yun-Tae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:34
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/14; H03M1/145; H03M1/361; H03M1/38; H03M1/46
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
124 words
A flash-successive approximation analog-to-digital converter for inputting an analog input signal and outputting n bits of digital output data which correspond to said analog input signal, comprising: an n/2 bit flash conversion circuit for sampling said analog input signal and outputting a first digital signal comprising the most significant n/2 bits of said digital output data which correspond to said analog input signal, and a first analog signal comprising an analog voltage level which corresponds to said first digital signal; and an n/2 bit successive approximation conversion circuit for subtracting said first analog signal from said analog input signal, and for outputting a second digital word comprising the least significant n/2 bits of said digital output data which corresponds to said analog input signal.
Claim 2
Dependent Claim
124 words
A flash-successive approximation analog-to-digital converter for inputting an analog input signal and outputting n bits of digital output data which correspond to said analog input signal, comprising: an n/2 bit flash conversion circuit for sampling said analog input signal and outputting a first digital signal comprising the most significant n/2 bits of said digital output data which correspond to said analog input signal, and a first analog signal comprising an analog voltage level which corresponds to said first digital signal; and an n/2 bit successive approximation conversion circuit for subtracting said first analog signal from said analog input signal, and for outputting a second digital word comprising the least significant n/2 bits of said digital output data which corresponds to said analog input signal.
Claim 3
Dependent Claim
99 words
The flash-successive approximation analog-to-digital converter according to claim 1 wherein said n/2 bit flash conversion circuit further comprises, sample and hold means for sampling an analog input signal and for outputting a sampled voltage level; an n/2 bit flash converter for converting said analog voltage level into said first digital signal comprising the most significant n/2 bits of said digital output data which correspond to said analog input signal; latch means for latching said first digital signal; and digital-to-analog conversion means for converting said first digital signal into said first analog signal which corresponds to said first digital signal.
Claim 4
Dependent Claim
137 words
The flash-successive approximation analog-to-digital converter according to claim 1 or 2 wherein said n/2 bit successive approximation conversion circuit further comprises, subtraction means for subtracting said first analog signal from said sampled voltage level, and for outputting a second analog signal which corresponds to the least significant n/2 bits of said digital output data; a comparator for comparing said second analog signal with a third analog signal and for outputting a compared signal; successive approximation conversion means for inputting said compared signal and for outputting a second digital signal comprising the least significant n/2 bits of said digital output data which corresponds to said analog input signal; and digital-to-analog conversion means for inputting said second digital signal and for outputting said third analog signal which corresponds to the least significant n/2 bits of said digital output data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |