← Back to Patent Explorer
US5625359A Expired / Lapsed US ⏱️ 0.0 years remaining

Variable sample rate ADC

Assignee: Analog Devices Inc
•
Filing: 1995-06-06
•
Granted: 1997-04-29
•
Expires: 2015-06-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.

Inventors

  • 👤 James Wilson
  • 👤 Ronald A. Cellini
  • 👤 James M. Sobol

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 04:07
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/368; H03M3/37; H03M3/372; H03M3/50

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 80 words
A method for producing, from an analog input signal, digital samples at a predetermined sample rate, comprising the steps of: computing a frequency select signal corresponding to the predetermined sample rate; producing, from the frequency select signal, a noise-shaped clock signal; converting the analog input signal to digital samples at an oversampling rate equal to the frequency of the noise-shaped clock signal; and decimating the digital samples to reduce the rate of the digital samples to the predetermined sample rate.
Claim 2
Independent Claim 80 words
A method for producing, from an analog input signal, digital samples at a predetermined sample rate, comprising the steps of: computing a frequency select signal corresponding to the predetermined sample rate; producing, from the frequency select signal, a noise-shaped clock signal; converting the analog input signal to digital samples at an oversampling rate equal to the frequency of the noise-shaped clock signal; and decimating the digital samples to reduce the rate of the digital samples to the predetermined sample rate.
Claim 3
Dependent Claim 22 words
A method as claimed in claim 1 wherein the step of producing includes the step of sigma-delta modulating the frequency select signal.
Claim 4
Dependent Claim 33 words
A method as claimed in claim 2 wherein the step of producing also includes the step of adjusting the frequency of an input clock signal based on the sigma-delta modulated frequency select signal.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-04-28 2000-10-28 2001-04-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-04-28 2004-10-28 2005-04-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-04-28 2008-10-28 2009-04-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag