Anti-alias filtering apparatus for frequency domain measurements

Claim 2

An anti-alais filter apparatus comprising: an input terminal for receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at any of a plurality of sample rates selectively controlled by said control means, said selected sample rate (fhd s) being equal to at least twice said selected measurement bandwidth; a plurality of low-pas filter means connected to said input terminal and said control means, said low-pass filter means having a plurality of cut-off frequencies selectively controlled by said control cut-off frequencies selectively controlled by said control means to output a signal having a cut-off frequency at least as great as said selected measurement bandwidth; an analog-to-digital convertor ("ADC") connected to sample said signal output by said low-pass filter means and to output a digital representation of said signal at said sample rate controlled by said clock means; memory means to receive and store a plurality of said digital samples from said ADC; and a digital low-pass filter having an input to receive said samples from said memory means and an output providing a digital representation of said low frequency components of said samples within said selected measurement bandwidth.

Claim 3

The anti-alias filter apparatus of claim 1 further comprising memory bypass switching means for selectively connecting said output of said ADC to the input of said digital low-pass filter when said sample rate is less than a predetermined limit, and to transfer said samples stored in said memory to the input to said digital low-pass filter when said sample rate is greater than said limit.

Claim 4

The anti-alias filter apparatus of claim 1 further comprising a decimator connected to said output of said digital low-pass filter to output one sample from each series of K samples received from said digital low-pass filter, where K is a positive integer variably determined by said control means.

Claim 5

The anti-alias filter apparatus of claim 3 further comprising: a second memory to receive and store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said samples stored in said second memory.

Claim 6

The anti-alias filter apparatus of claim 3 wherein the decimation factor K of said decimator is determined by said control means such that f s /K is at least twice said selected measurement bandwidth.

Claim 7

An anti-alias filter apparatus comprising: an input terminal for receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at any of a plurality of sample rates selectively controlled by said control means, said selected sample rate (f s ) being equal to at least twice said selected measurement bandwidth; a plurality of low-pass filter means connected to said input terminal and said control means, said low-pass filter means having a plurality of cut-off frequencies selectively controlled by said control means to output a signal having a cut-off frequency at least as great as said selected measurement bandwidth; an analog-to-digital converter ("ADC") connected to sample said signal output by said low-pass filter means and to output a digital representation of said signal at said sample rate controlled by said clock means; a first memory means to receive and store a plurality of said digital samples from said ADC; a digital low-pass filter having an input to receive said samples from said first memory means and an output providing a digital representation of said low frequency components of said samples within said selected measurement bandwidth; a decimator connected to said output of said digital low-pass filter to output one sample from each series of K samples received from said digital low-pass filter, where K is a positive integer variably determined by said control means; a second memory means to receive and store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said samples stored in said second memory.

Claim 8

An anti-alias filter apparatus comprising: an input terminal for receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at any of a plurality of sample rates selectively controlled by said control means, said selected sample rate (f s ) being equal to at least twice said selected measurement bandwidth; a plurality of low-pass filter means connected to said input terminal and said control means, said low-pass filter means having a plurality of cut-off frequencies selectively controlled by said control means to output a signal having a cut-off frequency at least as great as said selected measurement bandwidth; an analog-to-digital converter ("ADC") connected to sample said signal output by said low-pass filter means and to output a digital representation of said signal at said sample rate controlled by said clock means; a first memory means to receive and store a plurality of said digital samples from said ADC; a digital low-pass filter having an input to receive said samples from said first memory means and an output providing a digital representation of said low frequency components of said samples within said selected measurement bandwidth; a decimator connected to said output of said digital low-pass filter to output one sample from each series of K samples received from said digital low-pass filter, where K is a positive integer variably determined by said control means; a second memory means to receive and store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said samples stored in said second memory.

Claim 9

The anti-alias filter apparatus of claim 6 further comprising memory bypass switching means for selectively connecting said output of said ADC to the input of said digital low-pass filter when said sample rate is less than a predetermined limit, and to transfer said samples stored in said memory to the input of said digital low-pass filter when said sample rate is greater than said limit.

Claim 10

The anti-alias filter apparatus of claim 6 wherein the decimation factor K of said decimator is determined by said control means such that f s /K is at least twice said selected measurement bandwidth.

Claim 11

An anti-alias filter apparatus comprising: an input terminal or receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at either a high sample rate or a low sample rate selectively controlled by said control means, said selected sample rate (f s ) being equal to at least twice said selected measurement bandwidth; a first low-pass filter connected to said input terminal to output a signal having a cut-off frequency at least as great as the maximum measurement bandwidth; a second low-pass filter connected to said input terminal to output a signal having a predetermined cut-off frequency less than said cut-off frequency of said first low-pass filter; switching means controlled by said control means to select either said first low-pass filter or said second low-pass filter such that the cut-off frequency of the selected low-pass filter is at least as great as said selected measurement bandwidth; an analog-to-digital convertor ("ADC") connected to sample said signal output by said selected low-pass filter and to output a digital representation of said signal at said selected sample rate controlled by said clock means; a digital finite impulse response ("FIR") filter to receive a series of digital sample and to output a digital representation of said low frequency components of said samples within said selected measurement bandwidth, operation of said digital FIR filter being adjustably controlled by a number of filter coefficients determined by said control means; a first memory means to store a plurality of said digital samples from said ADC if said high sample rate is selected, and to subsequently output said stored samples to said digital FIR filter; a memory bypass switching means for connecting said samples output by said ADC to said digital FIR filter if said low sample rate is selected; a decimator connected to said output of said digital FIR filter to output one sample from each series of K samples received from said digital FIR filter where K is a positive integer determined by said control mean such that f s /K is at least twice said selected measurement bandwidth; a second memory means to store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said sample stored in said second memory.

Claim 12

An anti-alias filter apparatus comprising: an input terminal or receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at either a high sample rate or a low sample rate selectively controlled by said control means, said selected sample rate (f s ) being equal to at least twice said selected measurement bandwidth; a first low-pass filter connected to said input terminal to output a signal having a cut-off frequency at least as great as the maximum measurement bandwidth; a second low-pass filter connected to said input terminal to output a signal having a predetermined cut-off frequency less than said cut-off frequency of said first low-pass filter; switching means controlled by said control means to select either said first low-pass filter or said second low-pass filter such that the cut-off frequency of the selected low-pass filter is at least as great as said selected measurement bandwidth; an analog-to-digital convertor ("ADC") connected to sample said signal output by said selected low-pass filter and to output a digital representation of said signal at said selected sample rate controlled by said clock means; a digital finite impulse response ("FIR") filter to receive a series of digital sample and to output a digital representation of said low frequency components of said samples within said selected measurement bandwidth, operation of said digital FIR filter being adjustably controlled by a number of filter coefficients determined by said control means; a first memory means to store a plurality of said digital samples from said ADC if said high sample rate is selected, and to subsequently output said stored samples to said digital FIR filter; a memory bypass switching means for connecting said samples output by said ADC to said digital FIR filter if said low sample rate is selected; a decimator connected to said output of said digital FIR filter to output one sample from each series of K samples received from said digital FIR filter where K is a positive integer determined by said control mean such that f s /K is at least twice said selected measurement bandwidth; a second memory means to store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said sample stored in said second memory.

Claim 13

An anti-alias filter apparatus comprising: an input terminal for receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at either a high sample rate, a middle sample rate, or a low sample rate selectively controlled by said control means, said selected sample rate (f s ) being equal to at least twice said selected measurement bandwidth; a first low-pass filter connected to said input terminal to output a signal having a cut-off frequency at least as great as the maximum measurement bandwidth; a second low-pass filter connected to said input terminal to output a signal having a predetermined cut-off frequency less than said cut-off frequency of said first low-pass filter; a third low-pass filter connected to said input terminal to output a signal having a predetermined cut-off frequency less than said cut-off frequency of said second low-pass filter; switching means controlled by said control means to select either said first low-pass filter, said second low-pass filter, or said third low-pass filter such that the cut-off frequency of the selected low-pass filter is at least as great as said selected measurement bandwidth; an analog-to-digital convertor ("ADC") connected to sample said signal output by said selected low-pass filter and to output a digital representation of said signal at said selected sample rate controlled by said clock means; a digital finite impulse response ("FIR") filter to receive a series of digital samples and to output a digital representation of said low frequency components of said samples within said selected measurement bandwidth, operation of said digital FIR filter being adjustably controlled by a number of filter coefficients determined by said control means; a filter memory means to store a plurality of said digital samples from said ADC if said low sample rate is not selected, and to subsequently output said stored samples to said digital FIR filter; a memory bypass switching means for connecting said sample output by said ADC to said digital FIR filter if said low sample rate is selected; a decimator connected to said output of said digital FIR filter to output one sample from each series of K samples received from said digital FIR filter, where K is a positive integer determined by said control mean such that f s /K is at least twice said selected measurement bandwidth; a second memory means to store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said samples stored in said second memory.

Claim 14

An anti-alias filter apparatus comprising: an input terminal for receiving an input signal having a number of frequency components; control means for selecting one of a predetermined plurality of measurement bandwidths; clock means for generating a series of clock pulses at either a high sample rate, a middle sample rate, or a low sample rate selectively controlled by said control means, said selected sample rate (f s ) being equal to at least twice said selected measurement bandwidth; a first low-pass filter connected to said input terminal to output a signal having a cut-off frequency at least as great as the maximum measurement bandwidth; a second low-pass filter connected to said input terminal to output a signal having a predetermined cut-off frequency less than said cut-off frequency of said first low-pass filter; a third low-pass filter connected to said input terminal to output a signal having a predetermined cut-off frequency less than said cut-off frequency of said second low-pass filter; switching means controlled by said control means to select either said first low-pass filter, said second low-pass filter, or said third low-pass filter such that the cut-off frequency of the selected low-pass filter is at least as great as said selected measurement bandwidth; an analog-to-digital convertor ("ADC") connected to sample said signal output by said selected low-pass filter and to output a digital representation of said signal at said selected sample rate controlled by said clock means; a digital finite impulse response ("FIR") filter to receive a series of digital samples and to output a digital representation of said low frequency components of said samples within said selected measurement bandwidth, operation of said digital FIR filter being adjustably controlled by a number of filter coefficients determined by said control means; a filter memory means to store a plurality of said digital samples from said ADC if said low sample rate is not selected, and to subsequently output said stored samples to said digital FIR filter; a memory bypass switching means for connecting said sample output by said ADC to said digital FIR filter if said low sample rate is selected; a decimator connected to said output of said digital FIR filter to output one sample from each series of K samples received from said digital FIR filter, where K is a positive integer determined by said control mean such that f s /K is at least twice said selected measurement bandwidth; a second memory means to store a plurality of said samples output by said decimator; and means for generating a frequency domain measurement of said samples stored in said second memory.