Method and system for assigning a direct memory access priority in a packetized data communications interface device

Claim 3

The method of claim 1, wherein said shifting step comprises the step of shifting DMA channel upon said boundary condition comprising a PCI transfer complete state.

Claim 4

The method of claim 1, wherein said shifting step comprises the step of shifting DMA channel upon said boundary condition comprising a receive channel writing data into a receive FIFO.

Claim 5

The method of claim 1, wherein said shifting step comprises the step of shifting DMA channel execution upon said boundary condition comprising a DMA channel waiting for received data.

Claim 6

The method of claim 1, further comprising the step of generating a current DMA channel signal for designating the currently active DMA channel.

Claim 7

The method of claim 1, further comprising the step of shifting DMA channel execution according to a subset of available pending channels.

Claim 8

The method of claim 1, further comprising the step of shifting DMA channel execution according to a programmably selectable subset of DMA channels.

Claim 9

The method of claim 1, wherein said shifting step comprises the step of shifting DMA execution upon said boundary condition comprising a DMA channel waiting for activity external to said DMA channel to occur.

Claim 10

A direct memory access (DMA) channel circuit within a PCI-serial bus interface device for assigning a priority to a DMA channel for a packet data transfer device associated with a particular data packet being transferred, to provide for immediate scheduling of said DMA channel to optimize data transfer behavior, said DMA channel circuit comprising: DMA channel determining circuitry for determining the DMA channel associated with the data packet on a physical media interface for the data packet transfer device; microprocessor DMA channel instructions for supplying to a DMA arbitration logic circuit information relating to the DMA channel number associated with the data packet on the physical media interface, with said DMA channel number assigned a highest priority value; microprocessor DMA channel service instructions for continuing to service execution of the associated DMA channel until a predetermined boundary condition exists; and shifting circuitry for shifting DMA engine execution to a DMA channel having the highest priority upon determining the occurrence of the boundary condition.

Claim 11

A direct memory access (DMA) channel circuit within a PCI-serial bus interface device for assigning a priority to a DMA channel for a packet data transfer device associated with a particular data packet being transferred, to provide for immediate scheduling of said DMA channel to optimize data transfer behavior, said DMA channel circuit comprising: DMA channel determining circuitry for determining the DMA channel associated with the data packet on a physical media interface for the data packet transfer device; microprocessor DMA channel instructions for supplying to a DMA arbitration logic circuit information relating to the DMA channel number associated with the data packet on the physical media interface, with said DMA channel number assigned a highest priority value; microprocessor DMA channel service instructions for continuing to service execution of the associated DMA channel until a predetermined boundary condition exists; and shifting circuitry for shifting DMA engine execution to a DMA channel having the highest priority upon determining the occurrence of the boundary condition.

Claim 12

The DMA channel circuits of claim 9, wherein said shifting circuitry comprises circuitry for shifting the DMA channel upon said boundary condition comprising a PCI transfer complete state.

Claim 13

The DMA channel circuit of claim 9, wherein said shifting circuitry comprises circuitry for shifting DMA channel upon said boundary condition comprising a receive channel writing data into a receive FIFO.

Claim 14

The DMA channel circuit of claim 9, wherein said shifting circuitry comprises circuitry for shifting DMA channel execution upon said boundary condition comprising a DMA channel waiting for received data.

Claim 15

The DMA channel circuit of claim 9, further comprising generating circuitry, for generating a current DMA channel signal for designating the currently active DMA channel.

Claim 16

The DMA channel circuit of claim 9, further comprising DMA channel shifting circuitry for shifting DMA channel execution according to a subset of available pending channels.

Claim 17

The DMA channel circuit of claim 9, further comprising the circuitry for shifting DMA channel execution according to a programmably selectable subset of DMA channels.

Claim 18

The DMA channel circuit of claim 9, wherein said shifting step comprises the step of shifting the DMA channel execution upon said boundary condition comprising a DMA channel waiting for activity external to said DMA channel to occur.

Claim 19

A personal computer system, comprising: at least one peripheral employing a data packet transfer bus; a computer, said computer comprising: a host cpu comprising a PCI bus; and a PCI-interface device for providing an interface between said PCI bus and said peripheral, said PCI-interface device comprising a direct memory access (DMA) circuit for assigning DMA channel priority for a data packet transfer device associated with a particular data packet being transferred, to provide for immediate scheduling of said DMA channel to optimize data transfer behavior, said DMA channel circuit comprising: DMA channel determining circuitry for determining the DMA channel associated with the data packet on a physical media interface for the data packet transfer device; microprocessor DMA channel instructions for supplying to a DMA control logic circuit information relating to a DMA channel number associated with the data transfer currently active on the physical media interface, with said DMA channel number assigned as highest priority; microprocessor DMA channel service instructions for continuing to service the associated DMA channel for execution until a predetermined boundary condition exists; and shifting circuitry for shifting DMA engine execution to a DMA channel having the highest priority upon determining the occurrence of the boundary condition.

Claim 20

A personal computer system, comprising: at least one peripheral employing a data packet transfer bus; a computer, said computer comprising: a host cpu comprising a PCI bus; and a PCI-interface device for providing an interface between said PCI bus and said peripheral, said PCI-interface device comprising a direct memory access (DMA) circuit for assigning DMA channel priority for a data packet transfer device associated with a particular data packet being transferred, to provide for immediate scheduling of said DMA channel to optimize data transfer behavior, said DMA channel circuit comprising: DMA channel determining circuitry for determining the DMA channel associated with the data packet on a physical media interface for the data packet transfer device; microprocessor DMA channel instructions for supplying to a DMA control logic circuit information relating to a DMA channel number associated with the data transfer currently active on the physical media interface, with said DMA channel number assigned as highest priority; microprocessor DMA channel service instructions for continuing to service the associated DMA channel for execution until a predetermined boundary condition exists; and shifting circuitry for shifting DMA engine execution to a DMA channel having the highest priority upon determining the occurrence of the boundary condition.

Claim 21

The DMA channel circuit of claim 17, wherein said shifting circuitry comprises circuitry for shifting said DMA channel upon said boundary condition comprising a PCI transfer complete state.

Claim 22

The DMA channel circuit of claim 17, wherein said shifting circuitry comprises circuitry for shifting DMA channel upon said boundary condition comprising a receive channel writing data into a receive FIFO.

Claim 23

The DMA channel circuit of claim 17, wherein said shifting circuitry comprises circuitry for shifting DMA execution upon said boundary condition comprising a DMA channel waiting for received data.