Byte-mode and burst-mode data transfer mechanism for a high-speed serial interface

Claim 1

In a computer system having a memory including a direct memory access buffer area, and having a direct memory access controller and a serial communications controller connected to a serial port, a method in which one of a first telecommunications device and a second telecommunications device produces a transmit handshake signal to control transfer of transmit data from the memory to said one of the first telecommunications device and the second telecommunications device across a serial link that carries the transmit handshake signal, the method comprising the steps of: when the first telecommunication device is connected to the serial port: a) the first telecommunications device asserting the transmit handshake signal; b) the serial communications controller serially transmitting a unit of transmit data to the first telecommunications device across the serial link; c) the serial communications controller requesting a data unit from the direct memory access controller; d) the direct memory access controller transferring a data unit to the serial communications controller; e) the first telecommunication device de-asserting the transmit handshake signal; and f) repeating steps a) through e); whereby transfer of data is controlled by the first telecommunications device on a data-unit-by-data-unit basis; and when the second telecommunications device is connected to the serial port: g) the second telecommunications device asserting the transmit handshake signal; h) the serial communications controller serially transmitting a unit of transmit data to the second telecommunications device across the serial link; i) the serial communications controller requesting a data unit from the direct memory access controller; j) the direct memory access controller transferring a data unit to the serial communications controller; and k) repeating steps h) through j) until the second telecommunications device de-asserts the transmit handshake signal; whereby transfer of data is controlled by the second telecommunications device on a data burst basis.

Claim 3

An apparatus for transferring a stream of user data across a serial link between a memory in a computer system and a telecommunications device that produces a transmit handshake signal and a clock signal having a clock rate, both of which are carried by the serial link, the apparatus comprising: a direct memory access controller having access to said memory; a serial communications controller connected to the direct memory access controller and connected to the serial link, for handling bidirectional communications across the serial link at an average data rate in each direction less than said clock rate, the serial communications controller comprising: a transmit holding register connected to a transmit shift register, the transmit shift register being connected to the clock signal carried by the serial link and the transmit handshake signal, shifting of the transmit shift register being clocked by the clock signal and enabled when the transmit handshake signal is asserted; and a receive holding register connected to a receive shift register, the receive shift register being connected to the clock signal carried by the serial link and a reference potential, shifting of the receive shift register being clocked by the clock signal and continuously enabled by the reference potential.

Claim 4

An apparatus for transferring a stream of user data across a serial link between a memory in a computer system and a telecommunications device that produces a transmit handshake signal and a clock signal having a clock rate, both of which are carried by the serial link, the apparatus comprising: a direct memory access controller having access to said memory; a serial communications controller connected to the direct memory access controller and connected to the serial link, for handling bidirectional communications across the serial link at an average data rate in each direction less than said clock rate, the serial communications controller comprising: a transmit holding register connected to a transmit shift register, the transmit shift register being connected to the clock signal carried by the serial link and the transmit handshake signal, shifting of the transmit shift register being clocked by the clock signal and enabled when the transmit handshake signal is asserted; and a receive holding register connected to a receive shift register, the receive shift register being connected to the clock signal carried by the serial link and a reference potential, shifting of the receive shift register being clocked by the clock signal and continuously enabled by the reference potential.