US5418936A
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Double-buffered systems and methods
Assignee: Maxim Integrated Products Inc
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Filing: 1994-07-05
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Granted: 1995-05-23
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Expires: 2014-07-05
Abstract
Abstract A low-power timekeeping integrated circuit, using a double-buffered memory architecture: The user can freely read from user memory at any time, and an internal clock periodically updates a set of timekeeping registers. Transfer from the timekeeping registers to user memory (for update of the data) is performed as a block transfer, asynchronously and invisibly to the user. A special timing-window requirement is used to avoid access collision problems: each edge of the one-hertz oscillator signal is delayed slightly, and it is the delayed signal which actually clocks the update to the timekeeping registers. After a further small delay (long enough to allow for worst-case ripple-through delays in the timekeeping registers), a latched signal (NO -- RIPPLE, in the presently preferred embodiment) is driven active. The signal NO -- RIPPLE shows that any rippling has been completed and that access is safe. Thus, transfer will occur or not, but will never be cut short. When the user attempts to access the chip, the logic signal NO -- RIPPLE is sampled. If NO -- RIPPLE is not active, no transfers from timekeeping registers to the user memory is permitted, for as long as the user is accessing the chip. Whenever the user finishes an access, an update is automatically activated. Thus, in this scheme, the chip logic, while avoiding any updating during an access, will always provide the most current data into the user accessible registers, whenever possible.
Inventors
- 👤 Louis Rodriguez
- 👤 Kevin E. Deierling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:24
CPC Classifications
G; G04; G04G; G04G99/00; G06; G06F; G06F1/00; G06F1/04; G06F1/14; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
264 words
A system, comprising: an oscillator connected to provide a plurality of output pulses at a substantially regular interval; a counter chain; user memory connected to be read from or written to; transfer logic coupling said user memory to said counter chain, said transfer logic configured to selectively transfer at least one bit of said user memory onto at least one corresponding bit location of said counter chain or to selectively transfer at least one bit of said counter chain onto at least one corresponding bit location of said user memory; first delay circuitry coupled to receive said plurality of output pulses from said oscillator, said first delay circuitry generates a plurality of first delayed pulses corresponding to said plurality of output pulses, so that each first delayed pulse of said plurality of first delayed pulses corresponds to an output pulse of said plurality of output pulses, said first delay circuitry coupled to said counter chain to send said plurality of first delayed pulses to said counter chain in order to clock said counter chain; second delay circuitry coupled to receive said plurality of first delayed pulses from said first delay circuitry, said second delay circuitry generates a plurality of second delayed pulses corresponding to said plurality of first delayed pulses, so that each second delayed pulse of said plurality of second delayed pulses corresponds to a first delayed pulse of said plurality of first delayed pulses, said second delay circuitry coupled to said transfer logic to send said plurality of second delayed pulses to said transfer logic in order to clock said transfer logic.
Claim 2
Independent Claim
264 words
A system, comprising: an oscillator connected to provide a plurality of output pulses at a substantially regular interval; a counter chain; user memory connected to be read from or written to; transfer logic coupling said user memory to said counter chain, said transfer logic configured to selectively transfer at least one bit of said user memory onto at least one corresponding bit location of said counter chain or to selectively transfer at least one bit of said counter chain onto at least one corresponding bit location of said user memory; first delay circuitry coupled to receive said plurality of output pulses from said oscillator, said first delay circuitry generates a plurality of first delayed pulses corresponding to said plurality of output pulses, so that each first delayed pulse of said plurality of first delayed pulses corresponds to an output pulse of said plurality of output pulses, said first delay circuitry coupled to said counter chain to send said plurality of first delayed pulses to said counter chain in order to clock said counter chain; second delay circuitry coupled to receive said plurality of first delayed pulses from said first delay circuitry, said second delay circuitry generates a plurality of second delayed pulses corresponding to said plurality of first delayed pulses, so that each second delayed pulse of said plurality of second delayed pulses corresponds to a first delayed pulse of said plurality of first delayed pulses, said second delay circuitry coupled to said transfer logic to send said plurality of second delayed pulses to said transfer logic in order to clock said transfer logic.
Claim 3
Dependent Claim
52 words
The system of claim 1, wherein said second delay circuitry adds an additional delay to each first delayed pulses of said plurality of first delayed pulses while generating said plurality of second delayed pulses, said additional delay being at least equal to a worst-case time required for said counter chain to stabilize.
Claim 4
Dependent Claim
45 words
The system of claim 1, wherein said transfer logic has an associated time to transfer information between said counter chain and said user memory and said first delay circuitry generates said first delayed pulse with a delay which is at least equal to said time.
Claim 5
Dependent Claim
40 words
The system of claim 1, wherein said second delay circuitry adds an additional delay having a range of 10-100 nanoseconds to each first delayed pulse of said plurality of first delayed pulses while generating said plurality of second delayed pulses.
Claim 6
Dependent Claim
20 words
The system of claim 1, wherein said first delay circuitry and said second delay circuitry are combined into one circuit.
Claim 7
Dependent Claim
20 words
The system of claim 1, wherein said first delay circuitry and said second delay circuitry are separate from one another.
Claim 8
Dependent Claim
56 words
The system of claim 1, wherein said oscillator comprises an analog oscillator and a divider circuit, said analog oscillator produces said output pulse(s) having a first frequency, said divider circuit connected to reduce said first frequency of said output pulse(s) to a second frequency, said second frequency less than said first frequency of said analog oscillator.
Claim 9
Dependent Claim
48 words
The system of claim 1, wherein said oscillator comprises an analog oscillator and a divider circuit, said analog oscillator to produce said output pulse(s) having a first frequency, said divider circuit connected to reduce said first frequency of said plurality of output pulses to less than 1000 Hz.
Claim 10
Dependent Claim
49 words
The system of claim 1, wherein said oscillator comprises an analog oscillator and a divider circuit, said analog oscillator to produce said plurality of output pulses having a first frequency, said divider circuit connected to reduce said first frequency of said plurality of output pulses to approximately 1 Hz.
Claim 11
Dependent Claim
48 words
The system of claim 1, wherein said oscillator, said counter chain, said user memory, said transfer logic, said first delay circuitry, and said second delay circuitry are integrated onto a single integrated chip, wherein said oscillator comprises an analog oscillator that is stabilized by an off-chip resonant crystal.
Claim 12
Dependent Claim
48 words
The system of claim 1, wherein said transfer logic suppresses transferring an output from said counter chain onto said corresponding bit location(s) of said user memory whenever, after said oscillator generates an output pulse of said plurality of output pulses, said second delayed pulse has not yet occurred.
Claim 13
Dependent Claim
25 words
The system of claim 1, further comprising an input/output buffer connected to provide a bidirectional data pathway to and from user memory of said system.
Claim 14
Dependent Claim
12 words
The system of claim 1, wherein said system is a timekeeping system.
Claim 15
Dependent Claim
17 words
The system of claim 1, wherein said plurality of output pulses generated by said oscillator is asynchronous.
Claim 16
Dependent Claim
14 words
The system of claim 1, wherein said user memory comprises a plurality of latches.
Claim 17
Dependent Claim
55 words
The system of claim 1, wherein said transfer logic is parallel so that transferring said bit(s) of said user memory onto corresponding bit locations of said counter chain is parallel and selective and said transfer of said bit(s) of said counter chain onto said corresponding bit locations of said user memory is parallel and selective.
Claim 18
Dependent Claim
11 words
The system of claim 1, wherein said oscillator is a circuit.
Claim 19
Dependent Claim
21 words
The system of claim 1, wherein delays added by said first delayed circuitry and said second delayed circuitry are independently adjustable.
Claim 20
Dependent Claim
46 words
The system of claim 1, wherein each second delayed pulse of said plurality of second delayed pulses has a greater delay with respect to each output pulse of said plurality of said output pulse, than each first delayed pulse of said plurality of first delayed pulses.
Claim 21
Dependent Claim
51 words
The system of claim 1, wherein said transfer of said bit(s) of said user memory onto corresponding bit locations of said counter chain and said transfer of said bit(s) of said counter chain onto said corresponding bit locations of said user memory occur on a rising edge of said output pulse(s).
Claim 22
Dependent Claim
11 words
The system of claim 1, wherein said counter chain is synchronous.
Claim 23
Dependent Claim
14 words
The system of claim 1, wherein said system is embodied in an integrated circuit.
Claim 24
Dependent Claim
33 words
The system of claim 1, wherein said first delay circuitry comprises at least three inverters coupled together in series and said second delay circuitry comprises at least two inverters coupled together in series.
Claim 25
Dependent Claim
266 words
A doubled-buffered system for timekeeping systems, comprising: an oscillator to provide a plurality of output pulses at a substantially regular interval; a counter chain; user memory, said user memory being read from or written to; transfer logic coupling said user memory to said counter chain, said transfer logic alternatively transferring at least one bit of said user memory onto at least one corresponding bit location of said counter chain or transfering at least one bit of said counter chain onto at least one corresponding bit location of said user memory; first delay circuitry coupled to receive said plurality of output pulses from said oscillator, said first delay circuitry generating a plurality of first delayed pulses corresponding to said plurality of output pulses, so that each first delayed pulse of said plurality of first delayed pulses corresponds to an output pulse of said plurality of output pulses, said first delay circuitry being coupled to said counter chain to send said plurality of first delayed pulses to said counter chain in order to clock said counter chain; and second delay circuitry coupled to receive said plurality of first delayed pulses from said first delay circuitry, said second delay circuitry generating a plurality of delayed pulses corresponding to said plurality of first delayed pulses, so that each second delayed pulse of said plurality of second delayed pulses corresponds to a first delayed pulse of said plurality of first delayed pulses, said second delay circuitry being coupled to said transfer logic to send said plurality of second delayed pulses to said transfer logic in order to clock said transfer logic.
Claim 26
Dependent Claim
266 words
A doubled-buffered system for timekeeping systems, comprising: an oscillator to provide a plurality of output pulses at a substantially regular interval; a counter chain; user memory, said user memory being read from or written to; transfer logic coupling said user memory to said counter chain, said transfer logic alternatively transferring at least one bit of said user memory onto at least one corresponding bit location of said counter chain or transfering at least one bit of said counter chain onto at least one corresponding bit location of said user memory; first delay circuitry coupled to receive said plurality of output pulses from said oscillator, said first delay circuitry generating a plurality of first delayed pulses corresponding to said plurality of output pulses, so that each first delayed pulse of said plurality of first delayed pulses corresponds to an output pulse of said plurality of output pulses, said first delay circuitry being coupled to said counter chain to send said plurality of first delayed pulses to said counter chain in order to clock said counter chain; and second delay circuitry coupled to receive said plurality of first delayed pulses from said first delay circuitry, said second delay circuitry generating a plurality of delayed pulses corresponding to said plurality of first delayed pulses, so that each second delayed pulse of said plurality of second delayed pulses corresponds to a first delayed pulse of said plurality of first delayed pulses, said second delay circuitry being coupled to said transfer logic to send said plurality of second delayed pulses to said transfer logic in order to clock said transfer logic.
Claim 27
Dependent Claim
52 words
The system of claim 24, wherein said second delay circuitry adds an additional delay to each first delayed pulse of said plurality of first delayed pulses while generating said plurality of second delayed pulses, said additional delay being at least equal to a worst-case time required for said counter chain to stabilize.
Claim 28
Dependent Claim
49 words
The system of claim 24, wherein said transfer logic has an associated time to transfer information between said counter chain and said user memory and said first delay circuitry generates said plurality of first delayed pulse by adding a time delay which is at least equal to said time.
Claim 29
Dependent Claim
40 words
The system of claim 24, wherein said second delay circuitry adds an additional delay having a range of 10-100 nanoseconds to each first delayed pulse of said plurality of first delayed pulses while generating said plurality of second delayed pulses.
Claim 30
Dependent Claim
20 words
The system of claim 24, wherein said first delay circuitry and said second delay circuitry are combined into one circuit.
Claim 31
Dependent Claim
20 words
The system of claim 24, wherein said first delay circuitry and said second delay circuitry are separate from one another.
Claim 32
Dependent Claim
73 words
The system of claim 24, wherein said oscillator comprises an analog oscillator and a divider circuit, said analog oscillator producing said plurality of output pulses having a first frequency, said divider circuit being coupled to receive said plurality of output pulses from said analog oscillator, said divider circuit reducing said first frequency of said output pulse(s) to a second frequency, said second frequency being less than said first frequency of said analog oscillator.
Claim 33
Dependent Claim
27 words
The system of claim 30, wherein said divider circuit is configured to reduce said first frequency of said plurality of output pulses to less than 1000 Hz.
Claim 34
Dependent Claim
25 words
The system of claim 30, said divider circuit being configured to reduce said first frequency of said plurality of output pulses to approximately 1 Hz.
Claim 35
Dependent Claim
49 words
The system of claim 24, wherein said oscillator, said counter chain, said user memory, said transfer logic, said first delay circuitry, and said second delay circuitry are integrated onto a single integrated chip, and wherein said oscillator comprises an analog oscillator that is stabilized by an off-chip resonant crystal.
Claim 36
Dependent Claim
48 words
The system of claim 24, wherein said transfer logic suppresses transferring an output from said counter chain onto said corresponding bit locations of said user memory whenever said second delayed pulse has not yet occurred, after said oscillator generates an output pulse of said plurality of output pulses.
Claim 37
Dependent Claim
25 words
The system of claim 24, further comprising an input/output buffer connected to provide a bidirectional data pathway to and from user memory of said system.
Claim 38
Dependent Claim
17 words
The system of claim 24, wherein said plurality of output pulses generated by said oscillator is asynchronous.
Claim 39
Dependent Claim
14 words
The system of claim 1, wherein said user memory comprises a plurality of latches.
Claim 40
Dependent Claim
55 words
The system of claim 24, wherein said transfer logic is parallel so that transferring said bit(s) of said user memory onto corresponding bit locations of said counter chain is parallel and selective and said transfer of said bit(s) of said counter chain onto said corresponding bit locations of said user memory is parallel and selective.
Claim 41
Dependent Claim
21 words
The system of claim 24, wherein delays added by said first delay circuitry and said second delay circuitry are independently adjustable.
Claim 42
Dependent Claim
46 words
The system of claim 24, wherein each second delayed pulse of said plurality of second delayed pulses has a greater delay with respect to each output pulse of said plurality of said output pulse, than each first delayed pulsed of said plurality of first delayed pulses.
Claim 43
Dependent Claim
51 words
The system of claim 24, wherein said transfer of said bit(s) of said user memory onto corresponding bit locations of said counter chain and said transfer of said bit(s) of said counter chain onto said corresponding bit locations of said user memory occurs on a rising edge of said output pulses.
Claim 44
Dependent Claim
11 words
The system of claim 24, wherein said counter chain is synchronous.
Claim 45
Dependent Claim
33 words
The system of claim 24, wherein said first delay circuitry comprises at least three inverters coupled together in series and said second delay circuitry comprises at least two inverters coupled together in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-22 | 1998-11-21 | 1999-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-22 | 2002-11-21 | 2003-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-22 | 2006-11-21 | 2007-05-23 | $7700.00 | Window Closed / Lapsed |