US5805778A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DMA controller for DMA transferring image data for one page without increasing a burden on a CPU
Assignee: Ricoh Co Ltd
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Filing: 1995-10-10
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Granted: 1998-09-08
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Expires: 2015-10-10
Abstract
Abstract A DMA transfer controller for DMA transferring one page of image data without increasing a burden on a CPU is provided with address holders for holding addresses for each of a plurality of DMA channels. An address selector selects an address for an operating DMA channel and an address adding value prescriber prescribes an address adding value at an arbitrary value. An address adding value selector selects an address adding value between prescribed address adding values and a fixed adding value and an address adder adds such an address adding value to an output address value. A latch address selector selects an initial address value when initializing a DMA transfer and an address value produced after an address adding value has been added for providing such an address to address holders when DMA transfer is started.
Inventors
- 👤 Takao Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:26
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/32; H04N1/32358; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06T; G06T1/00; G06T1/60; H04N2201/00; H04N2201/32; H04N2201/3285; H04N2201/3287
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
105 words
A DMA controller which controls a DMA transfer for a plurality of DMA channels of image data between a peripheral equipment and a storage device without involving a central processing unit, comprising: address generating means for generating addresses for each DMA channel by adding consecutively an address adding value prescribed beforehand to an initial address value and following consecutive address values, wherein the address generating means includes a respective address holding means for each DMA channel and an address selecting means for selecting one of said address holding means; and address adding value prescribing means for prescribing said address adding value at an arbitrary value.
Claim 2
Dependent Claim
105 words
A DMA controller which controls a DMA transfer for a plurality of DMA channels of image data between a peripheral equipment and a storage device without involving a central processing unit, comprising: address generating means for generating addresses for each DMA channel by adding consecutively an address adding value prescribed beforehand to an initial address value and following consecutive address values, wherein the address generating means includes a respective address holding means for each DMA channel and an address selecting means for selecting one of said address holding means; and address adding value prescribing means for prescribing said address adding value at an arbitrary value.
Claim 3
Dependent Claim
39 words
The DMA controller according to claim 1, further comprising address adding value switching means for switching said address adding value between the fixed adding value prescribed beforehand and the arbitrary value prescribed by said address adding value prescribing means.
Claim 4
Dependent Claim
41 words
The DMA controller according to claim 2, wherein said address adding value prescribing means are plural in number and said address adding value switching means switches said address adding value among those prescribed by said plural address adding value prescribing means.
Claim 5
Dependent Claim
23 words
The DMA controller according to claim 2, wherein said address adding value switching means switches said address adding value for each DMA channel.
Claim 6
Dependent Claim
31 words
The DMA controller according to claim 2, wherein said address adding value switching means switches said address adding value every time a transfer of a predetermined volume of data is completed.
Claim 7
Dependent Claim
145 words
An image processing system which is equipped with a DMA controller which controls a DMA transfer for a plurality of DMA channels of image data between a peripheral equipment and a storage device without involving a central processing unit, comprising: address generating means for generating addresses for each DMA channel by consecutively adding a fixed address adding value prescribed beforehand to an initial address value and following consecutive address values, wherein the address generating means includes a respective address holding means for each DMA channel and an address selecting means for selecting one of said address holding means; address adding value prescribing means for prescribing said address adding value at an arbitrary value; and address adding value switching means for switching said address adding value between the fixed adding value prescribed beforehand and the arbitrary adding value prescribed by said address adding value prescribing means.
Claim 8
Dependent Claim
145 words
An image processing system which is equipped with a DMA controller which controls a DMA transfer for a plurality of DMA channels of image data between a peripheral equipment and a storage device without involving a central processing unit, comprising: address generating means for generating addresses for each DMA channel by consecutively adding a fixed address adding value prescribed beforehand to an initial address value and following consecutive address values, wherein the address generating means includes a respective address holding means for each DMA channel and an address selecting means for selecting one of said address holding means; address adding value prescribing means for prescribing said address adding value at an arbitrary value; and address adding value switching means for switching said address adding value between the fixed adding value prescribed beforehand and the arbitrary adding value prescribed by said address adding value prescribing means.
Claim 9
Dependent Claim
23 words
The image processing system according to claim 6, wherein image data for one page constitutes one block of data for the DMA transfer.
Claim 10
Dependent Claim
17 words
The image processing system according to claim 7, wherein said image processing system is a facsimile apparatus.
Claim 11
Dependent Claim
18 words
The image processing system according to claim 7, wherein said image processing system is a digital copying machine.
Claim 12
Dependent Claim
92 words
A DMA controller which controls a DMA transfer for a plurality of DMA channels of image data between a peripheral equipment and a storage device, comprising: an address generator generating addresses for each DMA channel by adding consecutively an address adding value to an initial address value and following consecutive address values, wherein the address generator includes a respective address holder for each DMA channel and an address selector selecting one of said address holder; and a first address adding value prescriber prescribing said address adding value at a first arbitrary value.
Claim 13
Dependent Claim
92 words
A DMA controller which controls a DMA transfer for a plurality of DMA channels of image data between a peripheral equipment and a storage device, comprising: an address generator generating addresses for each DMA channel by adding consecutively an address adding value to an initial address value and following consecutive address values, wherein the address generator includes a respective address holder for each DMA channel and an address selector selecting one of said address holder; and a first address adding value prescriber prescribing said address adding value at a first arbitrary value.
Claim 14
Dependent Claim
37 words
The DMA controller according to claim 10, further comprising an address adding value switch switching said address adding value between a predetermined fixed adding value and the arbitrary value prescribed by said first address adding value prescriber.
Claim 15
Dependent Claim
54 words
The DMA controller according to claim 11, further comprising a second address adding value prescriber prescribing said address adding value at a second arbitrary value, and said address adding value switch switching said address adding value between the first and second arbitrary values prescribed by said respective first and second address adding value prescribers.
Claim 16
Dependent Claim
22 words
The DMA controller according to claim 11, wherein said address adding value switch switches said address adding value for each DMA channel.
Claim 17
Dependent Claim
30 words
The DMA controller according to claim 11, wherein said address adding value switch switches said address adding value every time a transfer of a predetermined volume of data is completed.
Claim 18
Dependent Claim
23 words
The image processing system according to claim 10, wherein image data for one page constitutes one block of data for the DMA transfer.
Claim 19
Dependent Claim
17 words
The image processing system according to claim 15, wherein said image processing system is a facsimile apparatus.
Claim 20
Dependent Claim
18 words
The image processing system according to claim 15, wherein said image processing system is a digital copying machine.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |