Bridge circuit for preventing data incoherency by holding off propagation of data transfer completion interrupts until data clears the bridge circuit

Claim 2

A bridge circuit for providing an interface between a first bus and a second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

Claim 3

The bridge circuit of claim 1, wherein said interrupt control circuit continues to provide the first bus interrupt signal as long as the second bus provides the second bus interrupt signal.

Claim 4

A bridge circuit for providing an interface between a first bus and a second bus, wherein the second bus provides a plurality of second bus interrupt signals which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a plurality of data FIFOs for synchronizing data transfer between the first bus and the second bus, each data FIFO coupled between the first bus and the second bus, wherein each data FIFO provides an empty signal when said data FIFO is empty and wherein each data FIFO is associated with one of the plurality of second bus interrupt signals; and an interrupt control circuit receiving the plurality of second bus interrupt signals and said plurality of data FIFO empty signals and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when any of the second bus interrupt signals and the associated data FIFO empty signal are received, the first bus interrupt signal not provided when all of said second bus interrupt signals and said associated data FIFO empty signals are not received.

Claim 5

A bridge circuit for providing an interface between a first bus and a second bus, wherein the second bus provides a plurality of second bus interrupt signals which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a plurality of data FIFOs for synchronizing data transfer between the first bus and the second bus, each data FIFO coupled between the first bus and the second bus, wherein each data FIFO provides an empty signal when said data FIFO is empty and wherein each data FIFO is associated with one of the plurality of second bus interrupt signals; and an interrupt control circuit receiving the plurality of second bus interrupt signals and said plurality of data FIFO empty signals and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when any of the second bus interrupt signals and the associated data FIFO empty signal are received, the first bus interrupt signal not provided when all of said second bus interrupt signals and said associated data FIFO empty signals are not received.

Claim 6

The bridge circuit of claim 3, wherein said interrupt control circuit continues to provide the first bus interrupt signal as long as the second bus provides any one of the plurality of second bus interrupt signals and the associated empty signal are received.

Claim 7

The bridge circuit of claim 3, further comprising: an interrupt status register which indicates which of said plurality of second bus interrupt signals are pending, and wherein said interrupt control circuit is connected to said interrupt status register and provides a second bus interrupt pending signal to said interrupt status register for each of said plurality of second bus interrupt signals, said second bus interrupt pending signal indicating a pending interrupt when a respective second bus interrupt signal and the associated data FIFO empty signal are received.

Claim 8

The bridge circuit of claim 3, further comprising: an interrupt mask register for receiving indications as to which of said plurality of second bus interrupt signals is to be masked; and wherein the first bus interrupt signal provided when any of the non-masked second bus interrupt signals and the associated data FIFO empty signal are received said first bus interrupt signal not provided when any of the masked second bus interrupt signals and the associated data FIFO signal are received.

Claim 9

The bridge circuit of claim 3, wherein the second bus provides a plurality of general second bus interrupt signals not associated with said plurality of data FIFOs and a plurality of primary second bus interrupt signals associated with said plurality of data FIFOs said interrupt control circuit providing the first bus interrupt signal if any of said plurality of general second bus interrupt signals is asserted.

Claim 10

A bridge between a first bus and a second bus, comprising: a first bus master; a second bus master; a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

Claim 11

A bridge between a first bus and a second bus, comprising: a first bus master; a second bus master; a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

Claim 12

The bridge of claim 8, wherein the first bus master is a processor.

Claim 13

The bridge of claim 8, wherein the first bus master is a memory controller.

Claim 14

The bridge of claim 8, wherein the first bus master is an Application Specific Integrated Circuit (ASIC).

Claim 15

A bridge between a first bus and a second bus, comprising: a first bus master; a second bus master; a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a plurality of second bus interrupt signals which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a plurality of data FIFOs for synchronizing data transfer between the first bus and the second bus, each data FIFO coupled between the first bus and the second bus, wherein each data FIFO provides an empty signal when said data FIFO is empty and wherein each data FIFO is associated with one of the plurality of second bus interrupt signals; and an interrupt control circuit receiving the plurality of second bus interrupt signals and said plurality of data FIFO empty signals and providing the first bus interrupt signal and said plurality of data FIFO empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when any of the second bus interrupt signal and the associated data FIFO empty signal are received, the first bus interrupt signal not provided when all of said second bus interrupt signals and said associated data FIFO empty signals are not received.

Claim 16

A bridge between a first bus and a second bus, comprising: a first bus master; a second bus master; a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a plurality of second bus interrupt signals which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a plurality of data FIFOs for synchronizing data transfer between the first bus and the second bus, each data FIFO coupled between the first bus and the second bus, wherein each data FIFO provides an empty signal when said data FIFO is empty and wherein each data FIFO is associated with one of the plurality of second bus interrupt signals; and an interrupt control circuit receiving the plurality of second bus interrupt signals and said plurality of data FIFO empty signals and providing the first bus interrupt signal and said plurality of data FIFO empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when any of the second bus interrupt signal and the associated data FIFO empty signal are received, the first bus interrupt signal not provided when all of said second bus interrupt signals and said associated data FIFO empty signals are not received.

Claim 17

The bridge of claim 12, wherein said interrupt control circuit of said bridge circuit continues to provide the first bus interrupt signal as long as the second bus provides any one of the plurality of second bus interrupt signals and the associated empty signal are received.

Claim 18

The bridge of claim 12, further including: an interrupt status register which indicates which of said plurality of second bus interrupt signals are pending, and wherein said interrupt control circuit is connected to said interrupt status register and provides a second bus interrupt pending signal to said interrupt status register for each of said plurality of second bus interrupt signals, said second bus interrupt pending signal indicating a pending interrupt when a respective second bus interrupt signal and the associated data FIFO empty signal are received.

Claim 19

The bridge of claim 12, further including: an interrupt mask register for receiving indications as to which of said plurality of second bus interrupt signals is to be masked; and wherein the first bus interrupt signal is provided when any of the non-masked second bus interrupt signals and the associated data FIFO empty signal are received, said first bus interrupt signal not provided when any of the masked second bus interrupt signals and the associated data FIFO signal are received.

Claim 20

The bridge of claim 12, wherein the second bus provides a plurality of general second bus interrupt signals not associated with said plurality of data FIFOs and a plurality of primary second bus interrupt signals associated with said plurality of data FIFOs, said interrupt control circuit providing the first bus interrupt signal if any of said plurality of general second bus interrupt signals is asserted.

Claim 21

A disk array controller for coupling a disk array through an internal first bus of the controller to an external second bus comprising: a first bus internal to the controller; a first bus master; a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

Claim 22

A disk array controller for coupling a disk array through an internal first bus of the controller to an external second bus comprising: a first bus internal to the controller; a first bus master; a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

Claim 23

The disk array controller of claim 17, wherein the bridge circuit comprises: a plurality of data FIFOs for synchronizing data transfer between the first bus and the second bus, each data FIFO coupled between the first bus and the second bus, wherein each data FIFO provides an empty signal when said data FIFO is empty and wherein each data FIFO is associated with one of the plurality of second bus interrupt signals.

Claim 24

The disk array controller of claim 18, wherein the bridge circuit further comprises: an interrupt status register which indicates which of said plurality of second bus interrupt signals are pending, and wherein said interrupt control circuit is connected to said interrupt status register and provides second bus interrupt pending signals to said interrupt status register, a second bus interrupt pending signal provided for each of said plurality of second bus interrupt signals, said second bus interrupt pending signals indicating a pending interrupt when a respective second bus interrupt signal and the associated data FIFO empty signal are received.

Claim 25

The disk array controller of claim 18, wherein the bridge circuit further comprises: an interrupt mask register for receiving indications as to which of said plurality of second bus interrupt signals is to be masked; and wherein the first bus interrupt signal is provided when any of the non-masked second bus interrupt signals and the associated data FIFO empty signal are received, said first bus interrupt signal not provided when any of the masked second bus interrupt signals and the associated data FIFO signal are received.

Claim 26

The disk array control of claim 18, wherein the bridge circuit second bus provides a plurality of general second bus interrupt signals not associated with said plurality of data FIFOs and a plurality of primary second bus interrupt signals associated with said plurality of data FIFOs, said interrupt control circuit providing the first bus interrupt signal if any of said plurality of general second bus interrupt signals is asserted.

Claim 27

A computer system comprising: a disk drive array, comprising said disk array controller including: an internal first bus; a first bus master; a second bus internal to said disk array controller; said disk array controller further including: a bridge circuit for proving an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided with either said second bus interrupt signal is not received or said empty signal is not received.

Claim 28

A computer system comprising: a disk drive array, comprising said disk array controller including: an internal first bus; a first bus master; a second bus internal to said disk array controller; said disk array controller further including: a bridge circuit for proving an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising: a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty; and an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided with either said second bus interrupt signal is not received or said empty signal is not received.

Claim 29

The computer system of claim 22, wherein said bridge circuit of said disk array controller further comprises: an interrupt status register which indicates which of said plurality of second bus interrupt signals are pending, and wherein said interrupt control circuit is connected to said interrupt status register and provides a second bus interrupt pending signal for each of said plurality of second bus interrupt signals, said second bus interrupt pending signal indicating a pending interrupt when a respective second bus interrupt signal and the associated data FIFO empty signal are received.

Claim 30

The computer system of claim 22, wherein said bridge circuit of said disk array controller further comprises: an interrupt mask register for receiving indications which of said plurality of second bus interrupt signals is to be masked; and wherein the first bus interrupt signal is provided when any of the non-masked second bus interrupt signals and the associated data FIFO empty signal are received, said first bus interrupt signal not provided when any of the masked second bus interrupt signals and the associated data FIFO signal are received.

Claim 31

The computer system of claim 22, wherein the second bus provides a plurality of general second bus interrupt signals not associated with said plurality of data FIFOs and a plurality of primary second bus interrupt signals associated with said plurality of data FIFOs, said interrupt control circuit providing the first bus interrupt signal if any of said plurality of general second bus interrupt signals is asserted.