Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information

Claim 2

A multi-processor, multi-bus system comprising a first processor coupled to a first bus, a second processor of a type different from said first processor, said second processor being coupled to a second bus, said second bus of a type different from said first bus, the improvement wherein said system comprises: bus interface means for coupling said first bus to said second bus, said bus interface means comprising: a first-first-in first-out (FIFO) register stack for receiving data from said second bus and for transmitting data to said first bus; a second first-in-first-out (FIFO) register stack for receiving data from said first bus and for transmitting data to said second bus; control logic means coupled to said first and second FIFO register stacks and to said first and second buses for receiving control information from said first and second buses and for controlling the operation of said FIFO register stacks in response to said control information, said control logic means comprising interrupt logic means and status logic means; first receiver means coupled to said first FIFO register stack; first transmitter means coupled to said first bus for receiving first data and control information from said first bus and for transmitting said first data and control information to said second FIFO register stack; second receiver means coupled to said second FIFO register stack; and second transmitter means coupled to said second bus for receiving second data and control information from said second bus and for transmitting said second data and control information to said first FIFO register stack; wherein said first receiver means is for receiving said second data and control information from said second transmitter means and said second receiver means is for receiving said first data and control information from said first transmitter means.

Claim 3

The system recited in claim 1 and further comprising: a first plurality of peripheral units coupled to said first bus.

Claim 4

The system recited in claim 1 and further comprising: a second plurality of peripheral units coupled to said second bus.

Claim 5

In a multi-processor, multi-bus system comprising a first processor and a controller coupled to a first bus, said controller also being coupled to a first plurality of peripheral units; a second processor of a type different from said first processor, a second plurality of peripheral units, said second processor and said second plurality of peripheral units being coupled to a second bus, said second bus of a type different from said first bus; the improvement wherein said system comprises: first bus interface means for coupling said first plurality of peripheral units to said second processor, said first bus interface means being coupled between said first and second buses and comprising: a first first-in-first-out (FIFO) register stack for receiving data from said second bus and for transmitting data to said first bus; a first control logic means coupled to said first FIFO register stack for receiving first control information from said second bus and for controlling the operation of said first FIFO register stack in response to said first control information; first receiver means coupled to said second bus for receiving data and control information from said second bus; first transmitter means coupled to said second bus for transmitting data and control information to said second bus; and first interrupt means coupled to said first FIFO register stack and to said first receiver means for generating an interrupt signal to said second processor when said first FIFO register stack has been filled to a predetermined level; and second bus interface means for coupling said second plurality of peripheral units to said first processor, said second bus interface means being coupled between said first and second buses and comprising: a second first-in-first-out (FIFO) register stack for receiving data from said first bus and for transmitting data to said second bus; second control logic means coupled to said second FIFO register stack for receiving second control information from said second bus and for controlling the operation of said second FIFO register stack in response to said second control information; second receiver means coupled to said first bus for receiving data and control information from said first bus; second transmitter means coupled to said first bus for transmitting data and control information to said first bus; and second interrupt means coupled to said second FIFO register stack and to said second receiver means for generating an interrupt signal to said first processor when said second FIFO register stack has been filled to a predetermined level.

Claim 6

In a multi-processor, multi-bus system comprising a first processor and a controller coupled to a first bus, said controller also being coupled to a first plurality of peripheral units; a second processor of a type different from said first processor, a second plurality of peripheral units, said second processor and said second plurality of peripheral units being coupled to a second bus, said second bus of a type different from said first bus; the improvement wherein said system comprises: first bus interface means for coupling said first plurality of peripheral units to said second processor, said first bus interface means being coupled between said first and second buses and comprising: a first first-in-first-out (FIFO) register stack for receiving data from said second bus and for transmitting data to said first bus; a first control logic means coupled to said first FIFO register stack for receiving first control information from said second bus and for controlling the operation of said first FIFO register stack in response to said first control information; first receiver means coupled to said second bus for receiving data and control information from said second bus; first transmitter means coupled to said second bus for transmitting data and control information to said second bus; and first interrupt means coupled to said first FIFO register stack and to said first receiver means for generating an interrupt signal to said second processor when said first FIFO register stack has been filled to a predetermined level; and second bus interface means for coupling said second plurality of peripheral units to said first processor, said second bus interface means being coupled between said first and second buses and comprising: a second first-in-first-out (FIFO) register stack for receiving data from said first bus and for transmitting data to said second bus; second control logic means coupled to said second FIFO register stack for receiving second control information from said second bus and for controlling the operation of said second FIFO register stack in response to said second control information; second receiver means coupled to said first bus for receiving data and control information from said first bus; second transmitter means coupled to said first bus for transmitting data and control information to said first bus; and second interrupt means coupled to said second FIFO register stack and to said second receiver means for generating an interrupt signal to said first processor when said second FIFO register stack has been filled to a predetermined level.

Claim 7

In a multi-processor system comprising two processors each coupled to a different type of system bus, a method of interfacing between said two processors, said method comprising: using an N-bit control word to preface data control information to be passed from one processor to the other, said control word comprising an R-bit information portion, an S-bit destination portion, and a T-bit data type portion for indicating whether said R-bit portion contains data or control information, wherein N is 16, R is 8, S is 7, and T is 1 and wherein said T-bit portion indicates whether the R-bit portion contains control information, the R-bit portion indicates a multi-byte data transfer, and said S bit portion indicates the logical unit requesting the transfer; utilizing a 16-bit count word following said control word for indicating the number of data bytes which follow and that are to be transferred; and storing said data bytes in a plurality of 16-bit data words following said count word.

Claim 8

In a multi-processor system comprising two processors each coupled to a different type of system bus, a method of interfacing between said two processors, said method comprising: using an N-bit control word to preface data control information to be passed from one processor to the other, said control word comprising an R-bit information portion, an S-bit destination portion, and a T-bit data type portion for indicating whether said R-bit portion contains data or control information, wherein N is 16, R is 8, S is 7, and T is 1 and wherein said T-bit portion indicates whether the R-bit portion contains control information, the R-bit portion indicates a multi-byte data transfer, and said S bit portion indicates the logical unit requesting the transfer; utilizing a 16-bit count word following said control word for indicating the number of data bytes which follow and that are to be transferred; and storing said data bytes in a plurality of 16-bit data words following said count word.

Claim 9

The method recited in claim 5, wherein when T is a logical "one" it indicates that said R-bit portion contains a data command byte and when T is a logical "zero" it indicates that said R-bit portion contains a data byte.

Claim 10

The method recited in claim 5, wherein even-numbered bytes are placed in most significant bits 8-15 of said data words and odd-numbered bytes are placed in least significant bits 0-7 of said data word.

Claim 11

The method recited in claim 7, wherein if said count word indicates an odd number of data bytes to be transferred, the last one of said plurality of data words has logical "zeros" in bits 0-7 in order to indicate that the last data byte has been transferred.