Dynamic bus sizing of DMA transfers

Claim 2

A direct memory access (DMA) controller for controlling transfers of data between devices in an information handling system; the transfers being conducted, over an input/output (I/O) bus of the system, (a) between memory devices in the system, (b) between input/output (I/O) devices in the system, and (c) between memory and I/O devices in the system; the I/O bus connecting the DMA controller with the memory and I/O devices, and certain of the transfers being conducted during a plurality of consecutive cycles of operation of the I/O bus in which the DMA controller has continuous access to the I/O bus; the I/O bus being configured to be able to transfer plural bytes of data in parallel between the DMA controller operating during the consecutive bus cycles to receive data in parallel form, from a selected one of the memory and I/O devices (hereafter a "source" device) and to transfer received data in parallel form to another selected one of the memory and I/O devices (hereafter a "destination" device) via the I/O bus; the DMA controller comprising: a bus control circuit for receiving bus size information from a selected one of said source and destination devices at the beginning of each of the consecutive cycles of bus operation, said bus size information indicating the parallel data transfer capacity of the respective device relative to the bus; a look ahead circuit responsive to said bus size information received at the beginning of each of the consecutive bus cycles for providing a bus size control information signal necessary for completing a data transfer relative to said respective device in a respective bus cycle, said look ahead circuit including: a plurality of bus size control information generator circuits for generating a plurality of bus size control information signals, each bus size control information signal being necessary for completing data transfer for a corresponding bus size; and a bus size selection circuit for selecting one of said plurality of bus size control information signals in response to said bus size information; and a direct memory access control generator responsive to said bus size control information signal in each said bus cycle for controlling said bus, later in the respective bus cycle to transfer data in parallel over said bus, between the DMA controller and the respective device, with a parallel width corresponding to said bus size control information.

Claim 3

The DMA controller of claim 1, wherein said plurality of bus size control information generator circuits include an initial size control information generator circuit, said initial size control information generator circuit generating a size control information signal for an initial direct memory access transfer.

Claim 4

The DMA controller of claim 1 wherein said plurality of bus size control information generator circuits include an 8-bit bus size control information generator circuit, said 8-bit bus size control information generator circuit generating a size control information signal for transferring information via an eight bit wide bus.

Claim 5

The DMA controller of claim 1 wherein said plurality of bus size control information generator circuits include a 16-bit bus size control information generator circuit, said 16-bit bus size control information generator circuit generating a size control information signal for transferring information via a sixteen bit wide bus.

Claim 6

The DMA controller of claim 1 wherein said plurality of bus size control information generator circuits include a 32-bit bus size control information generator circuit, said 32-bit bus size control information generator circuit generating a size control information signal for transferring information via a 32 bit wide bus.

Claim 7

For a direct memory access (DMA) controller of an information handling system, look ahead apparatus, for generating bus size control information signals necessary for completing variable-width parallel data transfers through a parallel transfer I/O bus of said system, wherein said data transfers are conducted by said DMA controller between memory devices of said system, between I/O devices of said system, and between memory and I/O devices of said system; wherein said DMA controller is connected to said memory and I/O devices through said I/O bus; and wherein said DMA controller operates to conduct said data transfers in a plurality of consecutive data transfer cycles of said I/O bus, during which said DMA controller has continuous access to said I/O bus; said DMA controller operating during said consecutive bus cycles to receive data from a first selected one of said devices, via said I/O bus, and to transfer the same data to a second selected one of said devices via said I/O bus; said bus size control information signals being generated in each of said consecutive cycles in response to a bus size information function received by said DMA controller from a respective one of said first and second selected ones of said devices instantly in communication with said I/O bus, each said bus information function indicating a maximum parallel bus width that can be handled by the respective device; said parallel bus width corresponding to all or a predetermined fraction of the parallel data transfer capacity of said I/O bus; said DMA controller generating data transfer control information for the respective bus cycle based upon said bus size information functions and said control information signals, said look ahead apparatus comprising: means responsive to said bus size information function received from said selected first or second one of said devices, to generate a bus size select signal during each of said consecutive bus cycles; a plurality of bus size control information generator circuits for simultaneously generating a plurality of signals representing a plurality of different bus size data transfer control information signal functions, in each of said consecutive bus cycles, each said different bus size data transfer control information single function being necessary for completing a data transfer on said I/O bus with a corresponding one of a plurality of different parallel widths representing respectively different bus sizes; and a multiplexer circuit, said multiplexer circuit receiving said bus size select signal and said plurality of signals representing bus size data transfer control information signal functions and providing a selected one of said bus size data transfer control information signal functions in response to said bus size select signal.

Claim 8

For a direct memory access (DMA) controller of an information handling system, look ahead apparatus, for generating bus size control information signals necessary for completing variable-width parallel data transfers through a parallel transfer I/O bus of said system, wherein said data transfers are conducted by said DMA controller between memory devices of said system, between I/O devices of said system, and between memory and I/O devices of said system; wherein said DMA controller is connected to said memory and I/O devices through said I/O bus; and wherein said DMA controller operates to conduct said data transfers in a plurality of consecutive data transfer cycles of said I/O bus, during which said DMA controller has continuous access to said I/O bus; said DMA controller operating during said consecutive bus cycles to receive data from a first selected one of said devices, via said I/O bus, and to transfer the same data to a second selected one of said devices via said I/O bus; said bus size control information signals being generated in each of said consecutive cycles in response to a bus size information function received by said DMA controller from a respective one of said first and second selected ones of said devices instantly in communication with said I/O bus, each said bus information function indicating a maximum parallel bus width that can be handled by the respective device; said parallel bus width corresponding to all or a predetermined fraction of the parallel data transfer capacity of said I/O bus; said DMA controller generating data transfer control information for the respective bus cycle based upon said bus size information functions and said control information signals, said look ahead apparatus comprising: means responsive to said bus size information function received from said selected first or second one of said devices, to generate a bus size select signal during each of said consecutive bus cycles; a plurality of bus size control information generator circuits for simultaneously generating a plurality of signals representing a plurality of different bus size data transfer control information signal functions, in each of said consecutive bus cycles, each said different bus size data transfer control information single function being necessary for completing a data transfer on said I/O bus with a corresponding one of a plurality of different parallel widths representing respectively different bus sizes; and a multiplexer circuit, said multiplexer circuit receiving said bus size select signal and said plurality of signals representing bus size data transfer control information signal functions and providing a selected one of said bus size data transfer control information signal functions in response to said bus size select signal.

Claim 9

The apparatus of claim 6 wherein said plurality of bus size control information generator circuits include an initial size control information generator circuit, said initial size control information generator circuit generating a size control information signal for an initial direct memory access transfer.

Claim 10

The apparatus of claim 6 wherein said plurality of bus size control information generator circuits include an 8-bit bus size control information generator circuit, said 8-bit bus size control information generator circuit generating a size control information signal for transferring information via an eight bit wide bus.

Claim 11

The apparatus of claim 6 wherein said plurality of bus size control information generator circuits include a 16-bit bus size control information generator circuit, said 16-bit bus size control information generator circuit generating a size control information signal for transferring information via a sixteen bit wide bus.

Claim 12

The apparatus of claim 6 wherein said plurality of bus size control information generator circuits include a 32-bit bus size control information generator circuit, said 32-bit bus size control information generator circuit generating a size control information signal for transferring information via a 32 bit wide bus.