EP0333594A2
Expired / Lapsed
EP
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Direct memory access controller
Assignee: Fujitsu Ltd
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Filing: 1989-03-16
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Granted: —
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Expires: 2009-03-16
Abstract
Abstract A direct memory access controller coupled to a system bus (15) of a system for controlling data transfers through a channel, in which the operation is as follows. A request handler receives a transfer request (29a) generated by a device connected to the system bus. A transfer control information register (25) stores transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from the request handler. A temporary register (24) stores the transfer control information necessary for processing the next transfer request. A transfer control information setting circuit (27a, 27b, 28a, 28b) generates the transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in the transfer control information register during the data transfer by the present transfer request and then renewing the transfer control information and temporary registers with the generated transfer control information. A transfer execution circuit (31, 32) executes the actual data transfer through the system bus in accordance with the transfer control information registered in the temporary register, which is output to the system bus therefrom.
Inventors
- 👤 Takayoshi Taniai
- 👤 Yasuhiro Tanaka
- 👤 Tadashi Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 15:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
208 words
A direct memory access controller coupled to a system bus (15) of a system for controlling data transfers through a plurality of channels by a direct memory access, comprising request handling means (29a) for receiving a transfer request generated by a device connected to said system bus, and first register means (25) for storing transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from said request handling means, characterized in that said direct memory access controller comprises second register means (24) for storing said transfer control information necessary for processing the next transfer request, transfer control information setting means (27a, 27b, 28a, 28b) for generating said transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in said first register means (25) during the data transfer by the present transfer request and then renewing said first and second register means (25, 24) with the generated transfer control information; and transfer execution means (31, 32) far executing the actual data transfer through said system bus (15) in accordance with the transfer control information registered in the second register means (24), which is output to said system bus therefrom.
Claim 2
Dependent Claim
208 words
A direct memory access controller coupled to a system bus (15) of a system for controlling data transfers through a plurality of channels by a direct memory access, comprising request handling means (29a) for receiving a transfer request generated by a device connected to said system bus, and first register means (25) for storing transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from said request handling means, characterized in that said direct memory access controller comprises second register means (24) for storing said transfer control information necessary for processing the next transfer request, transfer control information setting means (27a, 27b, 28a, 28b) for generating said transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in said first register means (25) during the data transfer by the present transfer request and then renewing said first and second register means (25, 24) with the generated transfer control information; and transfer execution means (31, 32) far executing the actual data transfer through said system bus (15) in accordance with the transfer control information registered in the second register means (24), which is output to said system bus therefrom.
Claim 3
Dependent Claim
35 words
A direct memory access controller as claimed in claim 1, characterized in that each of said first and second register means (25, 24) comprises a register portion assigned to each of said plurality of channels.
Claim 4
Dependent Claim
47 words
A direct memory access controller as claimed in any of claims 1 and 2, characterized in that said transfer control information setting means (27a, 27b, 28a, 28b) starts to generate the transfer control information necessary for processing the next transfer request when the present transfer request occurs.
Claim 5
Dependent Claim
101 words
A direct memory access controller as claimed in any of claims 1 to 3, characterized in that said first register means (25) comprises, for each of said channels, a first register (CNTR) which registers a control information necessary for controlling the data transfer, a second register (BCR) which registers a byte count indicative of a amount of data to be transferred, and a third register (SAR, DAR) which registers address information relating to the data transfer, and that said control information, said byte count and said address information are said transfer control information to be registered in the first register means.
Claim 6
Dependent Claim
90 words
A direct memory access controller as claimed in any of claims 1 to 4, characterized in that said second register means (24) comprises, for each of said channels, a first register (CNTR′) which registers a control information necessary for controlling the data transfer by said next transfer request, and a second register (SAR′, DAR′) for registering address information relating to the data transfer by said next transfer request, and that said control information and said address information are the transfer control information to be registered in said second register means.
Claim 7
Dependent Claim
89 words
A direct memory access controller as claimed in any of claims 1 to 5, characterized in that said transfer control information setting means (27a, 27b, 28a, 28b) comprises a programmable logic array (28b) for controlling a sequence of the data transfer executed by said transfer execution means (31, 32) and a sequence of generating said transfer control information, a microsequencer (28a) for controlling said programmable logic array (28b), and an arithmetic and logic unit (27a, 27b) for generating said transfer control information necessary for processing the next transfer request.
Claim 8
Dependent Claim
60 words
A direct memory access controller as claimed in claim 6, characterized in that said transfer control information includes a control information (CNTR) necessary for controlling the data transfer, a byte count (BCR) indicative of an amount of data to be transferred, and an address information including a source address (SAR) and a destination address (DAR) relating to the data transfer.
Claim 9
Dependent Claim
34 words
A direct memory access controller as claimed in any of claims 1 to 7, characterized by further comprising an internal bus (50) to which said first and second register means (25, 24) are coupled.
Claim 10
Dependent Claim
29 words
A direct memory access controller as claimed in any of claims 1 to 8, characterized in that said second register means (24) is coupled to said system bus (15).
Claim 11
Dependent Claim
49 words
A direct memory access controller as claimed in claim 6, characterized in that said arithmetic and logic unit comprises a first arithmetic and logic unit (27a) for generating the source and destination addresses (SAR, DAR) and a second arithmetic and logic unit (27b) for generating the byte count (BCR).
Claim 12
Dependent Claim
56 words
A direct memory access controller as claimed in any of claims 1 to 10, characterized in that said transfer execution means comprises a data temporary register (32) for temporary storing data to be transferred, and a data swapper (31) which controls an exchange of data between said system bus (15) and said data temporary register (32).
References Cited (Backward Citations)
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