Look ahead bus transfer request

Claim 1

Improved access control logic for optimizing bus usage during DMA block data transfers across a non-dedicated bus between a main memory and an external device comprising: first and second buffers for storing incremental data units of a contiguous data block to be transferred; logic means for determining a total count of incremental data units of said contiguous data block to be transferred; circuit means for interconnecting said bus and said external device for transferring incremental data units of said contiguous data block from one of said first or second buffers therebetween; means for storing data into the other of said first or second buffers during the transfer by said circuit means; means, associated with said means for transferring, for updating said total count of incremental data units to be transferred at each transfer; and means responsive to said updating means for continually issuing a bus request for transfer of a subsequent incremental data unit from said contiguous data block before completion of transfer of a previous incremental data unit until said updating means indicates that the contiguous data block transfer is complete.

Claim 7

A method of minimizing idle time of a shared I/O bus during DMA transfer, over the bus to a main memory from an external device, of a contiguous block of data in increments of a fixed size comprising the steps of: a. loading data of said contiguous block from the external device alternately in a pair of buffers, each adapted to contain an internal number of said fixed size increments; b. determining the data amount content of each buffer; c. initiating whenever step b indicates one buffer is full, a DMA transfer of a fixed size increment of data from that full buffer to the I/O bus; d. issuing a bus request for each subsequent data transfer from that buffer before transfer of a previous increment of data is complete as long as a buffer contains data to be transferred; e. storing data into the other buffer until full; and f. sequentially repeating steps a through e until the contiguous block of data is transferred.

Claim 8

A method of minimizing idle time of a shared I/O bus during DMA transfer, over the bus to a main memory from an external device, of a contiguous block of data in increments of a fixed size comprising the steps of: a. loading data of said contiguous block from the external device alternately in a pair of buffers, each adapted to contain an internal number of said fixed size increments; b. determining the data amount content of each buffer; c. initiating whenever step b indicates one buffer is full, a DMA transfer of a fixed size increment of data from that full buffer to the I/O bus; d. issuing a bus request for each subsequent data transfer from that buffer before transfer of a previous increment of data is complete as long as a buffer contains data to be transferred; e. storing data into the other buffer until full; and f. sequentially repeating steps a through e until the contiguous block of data is transferred.

Claim 12

A method of providing back to back DMA data transfers to a system processor main memory from a serial communication link comprising the steps of sequentially: (i) loading data from said link in one of a first or second buffer; (ii) maintaining a current count of data in each of said buffers; (iii) initiating bus arbitration only in response to said current count indicating a full condition in one of said buffers; (iv) alternatingly placing data from said one of said buffers on a bus to said main memory; (v) storing data into the other of said buffers while data from said one of said buffers is placed on the bus; and (vi) repeating the preceding steps until an end of data condition is detected on said link.

Claim 13

A method of providing back to back DMA data transfers to a system processor main memory from a serial communication link comprising the steps of sequentially: (i) loading data from said link in one of a first or second buffer; (ii) maintaining a current count of data in each of said buffers; (iii) initiating bus arbitration only in response to said current count indicating a full condition in one of said buffers; (iv) alternatingly placing data from said one of said buffers on a bus to said main memory; (v) storing data into the other of said buffers while data from said one of said buffers is placed on the bus; and (vi) repeating the preceding steps until an end of data condition is detected on said link.