Capacitor on ultrathin semiconductor on insulator

Claim 2

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the channel is fully depleted for a gate bias voltage that has not surpassed a threshold voltage of the MOSFET structure.

Claim 3

The integrated circuit of claim 1 wherein the insulating substrate is sapphire.

Claim 4

The integrated circuit of claim 1 wherein the silicon layer is approximately 1000 Angstroms thick.

Claim 5

The integrated circuit of claim 1 wherein the silicon layer is in the range 100 Angstroms thick to 1500 Angstroms thick.

Claim 6

The integrated circuit of claim 1 wherein the source and drain extend to the insulating substrate.

Claim 7

The integrated circuit of claim 1 and further including a control voltage terminal coupled to one of said gate or said commonly connected source/drain.

Claim 8

The integrated circuit of claim 1 wherein the silicon layer surrounds the MOSFET structure.

Claim 9

The integrated circuit of claim 1 wherein the silicon layer is substantially less than 1000 Å thick and is greater than or equal to 100 Å thick.

Claim 10

The integrated circuit of claim 1 wherein the MOSFET structure is an n-type device structure.

Claim 11

The integrated circuit of claim 1 wherein the MOSFET structure is a p-type device structure.

Claim 12

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the MOSFET structure is an n-type device structure in which the channel is fully depleted for a negative gate bias voltage below a threshold voltage of the MOSFET structure.

Claim 13

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the MOSFET structure is an n-type device structure in which the channel is fully depleted for a negative gate bias voltage below a threshold voltage of the MOSFET structure.

Claim 14

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the MOSFET structure is a p-type devce structure in which the channel is fully depleted for a negative gate bias voltage above a threshold voltage of the MOSFET structure.

Claim 15

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including a channel, a source which includes a lightly doped source region adjacent to the channel, and a drain which includes a lightly doped drain region adjacent to the channel which are formed in said silicon layer and including a gate which overlays an oxide layer adjacent to said channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the MOSFET structure is a p-type devce structure in which the channel is fully depleted for a negative gate bias voltage above a threshold voltage of the MOSFET structure.

Claim 16

An integrated circuit capacitor comprising: an insulating substrate: a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first portion is fully depleted for a voltage applied to the first portion which has not surpassed a threshold voltge beyond which capitance of the capacitor structure sharply transitions.

Claim 17

An integrated circuit capacitor comprising: an insulating substrate: a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first portion is fully depleted for a voltage applied to the first portion which has not surpassed a threshold voltge beyond which capitance of the capacitor structure sharply transitions.

Claim 18

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first impurity is n-type and the second impurity is p-type and the silicon layer is thin enough to become fully depleted upon application of a voltage to the first contact which is below the threshold voltage of the capacitor structure.

Claim 19

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first impurity is n-type and the second impurity is p-type and the silicon layer is thin enough to become fully depleted upon application of a voltage to the first contact which is below the threshold voltage of the capacitor structure.

Claim 20

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first impurity is p-type and the second impurity is n-type and the silicon layer is thin enough to become fully depleted upon application of a voltage to the first contact which is above threshold voltage of the capacitor structure.

Claim 21

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween, and wherein said second portion includes opposed more lightly doped regions closer to the first portion and includes opposed more heavily doped regions farther from the first portion; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first impurity is p-type and the second impurity is n-type and the silicon layer is thin enough to become fully depleted upon application of a voltage to the first contact which is above threshold voltage of the capacitor structure.

Claim 22

The integrated circuit of claims 14 or 15 wherein the silicon layer is between 100 Å thick and 1500 Å thick.

Claim 23

The integrated circuit of claims 13, 14 and 15 wherein the second portion extends to the insulating substrate.

Claim 24

The integrated circuit of claim 13 wherein the first impurity type is one of p-type or n-type and the second impurity type is the other of p-type or n-type.

Claim 25

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including, a channel, a source adjacent to the channel, and a drain adjacent to the channel, which are formed in said silicon layer and including a gate which overlays the channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the channel is fully depleted for a gate bias voltage that has not surpassed a threshold voltage of the MOSFET structure.

Claim 26

An integrated circuit capacitor comprising: an insulating substrate; a layer of silicon formed on said insulating substrate; a MOSFET structure including, a channel, a source adjacent to the channel, and a drain adjacent to the channel, which are formed in said silicon layer and including a gate which overlays the channel; and a conductor interconnecting the source and drain so as to maintain them at a common potential; wherein the channel is fully depleted for a gate bias voltage that has not surpassed a threshold voltage of the MOSFET structure.

Claim 27

An integrated circuit capacitor comprising: an insulating substrate: a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first portion is filly depleted for a voltage applied to the first portion which has not surpassed a threshold voltge beyond which capitance of the capacitor structure gharply transitions.

Claim 28

An integrated circuit capacitor comprising: an insulating substrate: a layer of silicon formed on said insulating substrate; a capacitor structure which includes a first portion of the silicon layer doped with an impurity of a first type and which includes a second portion of the silicon layer which includes opposed sides doped with an impurity of a second type with the first portion disposed therebetween; and a first electrical contact to the first portion; and a second electrical contact to the second portion; wherein the first portion is filly depleted for a voltage applied to the first portion which has not surpassed a threshold voltge beyond which capitance of the capacitor structure gharply transitions.

Claim 29

The integrated circuit of claim 13, 14 or 15 wherein the silicon layer surrounds the second portion.

Claim 30

The integrated circuit of claim 13 wherein the first electrical contact includes a metal layer which overlays an oxide layer.

Claim 31

The integrated circuit of claim 13 wherein the first electrical connection includes a metal layer which overlays an oxide layer and the lightly doped regions extend partially beneath the first electrical connection.

Claim 32

The integrated circuit of claim 13, 14 or 15 wherein the insulating substrate is sapphire.

Claim 33

The integrated circuit of claim 13 wherein the layer of silicon is between 100 Å thick and 1500 Å thick.

Claim 34

The integrated circuit of claim 13 wherein the layer of silicon is approximately 1000 Å thick.

Claim 35

The integrated circuit of claim 13 wherein the layer of silicon is substantially less than 1000 Å thick and greater than or equal to 100 Å thick.

Claim 36

The integrated circuit of claim 11, or 12 wherein the source and drain extend to the insulating substrate.