Patent US5961634A successfully refreshed from Google Patents.
US5961634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reorder buffer having a future file for storing speculative instruction execution results
Assignee: Advanced Micro Devices Inc
•
Filing: 1998-07-13
•
Granted: 1999-10-05
•
Expires: 2018-07-13
Abstract
Abstract A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor. The reorder buffer tag (or instruction result, if the instruction has executed) of the last instruction in program order to update the register is stored in the future file. The reorder buffer provides the value (either reorder buffer tag or instruction result) stored in the storage location corresponding to a register when the register is used as a source operand for another instruction. Another advantage of the future file for microprocessors which allow access and update to portions of registers is that narrow-to-wide dependencies are resolved upon completion of the instruction which updates the narrower register.
Inventors
- 👤 Thang M. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3853; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
205 words
A reorder buffer comprising: an instruction storage configured to store instruction results corresponding to instructions, wherein said instruction results are stored in lines of storage, and wherein a line of storage is configured to store instruction results corresponding to a maximum number of concurrently dispatchable instructions, and wherein said maximum number is greater than one, and wherein a first line of storage is allocated upon dispatch of at least one instruction independent of a number of instructions concurrently dispatched; a future file configured to store a reorder buffer tag corresponding to a particular instruction, wherein said particular instruction is last, in program order, of the instructions represented within said instruction storage having a particular register as a destination operand, and wherein said future file is further configured to store a particular instruction result corresponding to said particular instruction when said particular instruction result is provided; and a control unit coupled to said instruction storage and to said future file, wherein said control unit is configured to allocate said first line of storage for said at least one instruction, and wherein said control unit is further configured to update said future file if said at least one instruction has said particular register as a destination operand.
Claim 2
Dependent Claim
205 words
A reorder buffer comprising: an instruction storage configured to store instruction results corresponding to instructions, wherein said instruction results are stored in lines of storage, and wherein a line of storage is configured to store instruction results corresponding to a maximum number of concurrently dispatchable instructions, and wherein said maximum number is greater than one, and wherein a first line of storage is allocated upon dispatch of at least one instruction independent of a number of instructions concurrently dispatched; a future file configured to store a reorder buffer tag corresponding to a particular instruction, wherein said particular instruction is last, in program order, of the instructions represented within said instruction storage having a particular register as a destination operand, and wherein said future file is further configured to store a particular instruction result corresponding to said particular instruction when said particular instruction result is provided; and a control unit coupled to said instruction storage and to said future file, wherein said control unit is configured to allocate said first line of storage for said at least one instruction, and wherein said control unit is further configured to update said future file if said at least one instruction has said particular register as a destination operand.
Claim 3
Dependent Claim
50 words
The reorder buffer as recited in claim 1 further comprising a second control unit coupled to receive instruction results and further coupled to said future file, wherein said second control unit is configured to update said future file with said particular instruction result upon receipt of said particular instruction result.
Claim 4
Dependent Claim
48 words
The reorder buffer as recited in claim 2 wherein said instruction storage is further configured to store a last in buffer indication for each instruction represented therein, wherein said last in buffer indication indicates that a corresponding instruction is last, in program order, to update said particular register.
Claim 5
Dependent Claim
47 words
The reorder buffer as recited in claim 3 wherein said second control unit is further configured to update said future file with said particular instruction result if said last in buffer indication indicates that said particular instruction is last, in program order, to update said particular register.
Claim 6
Dependent Claim
27 words
The reorder buffer as recited in claim 4 wherein said future file comprises a storage location configured to store either said reorder buffer tag or said result.
Claim 7
Dependent Claim
25 words
The reorder buffer as recited in claim 5 wherein said storage location is initialized to said reorder buffer tag upon dispatch of said particular instruction.
Claim 8
Dependent Claim
26 words
The reorder buffer as recited in claim 6 wherein said storage location is updated to said particular instruction result upon receipt of said particular instruction result.
Claim 9
Dependent Claim
25 words
The reorder buffer as recited in claim 1 wherein said future file comprises a plurality of storage locations corresponding to a plurality of said registers.
Claim 10
Dependent Claim
43 words
The reorder buffer as recited in claim 1 wherein said future file is configured to store a plurality of reorder buffer tags, wherein said plurality of reorder buffer tags correspond to a plurality of instructions which update different portions of said particular register.
Claim 11
Independent Claim
106 words
A method for operating a reorder buffer including a future file, the method comprising: allocating a storage location with said reorder buffer for storing an instruction result corresponding to an instruction; storing a reorder buffer tag indicative of said storage location into said future file responsive to said allocating; analyzing a last in buffer indication corresponding to said instruction upon receiving said instruction result; and updating said future file with said instruction result responsive to said analyzing determining that said last in buffer indication indicates that said instruction is last in said reorder buffer, in program order, to update a destination register specified by said instruction.
Claim 12
Independent Claim
106 words
A method for operating a reorder buffer including a future file, the method comprising: allocating a storage location with said reorder buffer for storing an instruction result corresponding to an instruction; storing a reorder buffer tag indicative of said storage location into said future file responsive to said allocating; analyzing a last in buffer indication corresponding to said instruction upon receiving said instruction result; and updating said future file with said instruction result responsive to said analyzing determining that said last in buffer indication indicates that said instruction is last in said reorder buffer, in program order, to update a destination register specified by said instruction.
Claim 13
Dependent Claim
55 words
The method as recited in claim 10 wherein said future file includes a plurality of storage locations corresponding to a plurality of registers including said destination register, and wherein said storing a reorder buffer tag comprises storing said reorder buffer tag into one of said plurality of storage locations which corresponds to said destination register.
Claim 14
Dependent Claim
53 words
The method as recited in claim 10 wherein said storage location allocated by said allocating comprises storage sufficient to store a maximum number of concurrently dispatchable instructions, and wherein said allocating comprises allocating said storage location even if a number of concurrently dispatched instructions including said instruction is less than said maximum number.
Claim 15
Dependent Claim
28 words
The method as recited in claim 12 further comprising determining that said instruction is last, in program order, among said concurrently dispatched instructions, to update said destination register.
Claim 16
Dependent Claim
37 words
The method as recited in claim 13 wherein said storing a reorder buffer tag is responsive to said determining that said instruction is last, in program order, among said concurrently dispatched instructions, to update said destination register.
Claim 17
Independent Claim
148 words
A method for operating a reorder buffer including a future file, the method comprising: allocating a line of storage for a plurality of concurrently dispatched instructions, said line of storage capable of storing instruction results corresponding to a maximum number of concurrently dispatchable instructions even if a number of said plurality of concurrently dispatched instructions is less than said maximum number, said maximum number being greater than one; accessing said future file to obtain source operands for each of said plurality of concurrently dispatched instructions; determining which one of said plurality of concurrently dispatched instructions is last, in program order, among said plurality of concurrently dispatched instructions to update a destination register specified by said one of said plurality of concurrently decoded instructions; and updating said future file to associate a reorder buffer tag identifying said one of said plurality of concurrently dispatched instructions with said destination register.
Claim 18
Independent Claim
148 words
A method for operating a reorder buffer including a future file, the method comprising: allocating a line of storage for a plurality of concurrently dispatched instructions, said line of storage capable of storing instruction results corresponding to a maximum number of concurrently dispatchable instructions even if a number of said plurality of concurrently dispatched instructions is less than said maximum number, said maximum number being greater than one; accessing said future file to obtain source operands for each of said plurality of concurrently dispatched instructions; determining which one of said plurality of concurrently dispatched instructions is last, in program order, among said plurality of concurrently dispatched instructions to update a destination register specified by said one of said plurality of concurrently decoded instructions; and updating said future file to associate a reorder buffer tag identifying said one of said plurality of concurrently dispatched instructions with said destination register.
Claim 19
Dependent Claim
263 words
A computer system comprising: a microprocessor including: a plurality of decode units configured to concurrently decode a plurality of instructions; and a reorder buffer coupled to receive said plurality of instructions from said plurality of decode units, said reorder buffer including: an instruction storage configured to store instruction results in lines of storage, wherein a line of storage is configured to store instruction results corresponding to a maximum number of concurrently dispatchable instructions, and wherein said maximum number is greater than one, and wherein a first line of storage is allocated to said plurality of instructions independent of a number of said plurality of instructions; a future file configured to store a reorder buffer tag corresponding to a particular instruction, wherein said particular instruction is last, in program order, of the instructions represented within said instruction storage having a particular register as a destination operand, and wherein said future file is further configured to store a particular instruction result corresponding to said particular instruction when said particular instruction result is provided; and a control unit coupled to said instruction storage and to said future file, wherein said control unit is configured to allocate said first line of storage for said plurality of instructions, and wherein said control unit is further configured to update said future file if at least one of said plurality of instructions has said particular register as a destination operand; and an input/output (I/O) device coupled to said microprocessor said I/O device configured to communicate between said computer system and another computer system to which said I/O device is coupled.
Claim 20
Dependent Claim
263 words
A computer system comprising: a microprocessor including: a plurality of decode units configured to concurrently decode a plurality of instructions; and a reorder buffer coupled to receive said plurality of instructions from said plurality of decode units, said reorder buffer including: an instruction storage configured to store instruction results in lines of storage, wherein a line of storage is configured to store instruction results corresponding to a maximum number of concurrently dispatchable instructions, and wherein said maximum number is greater than one, and wherein a first line of storage is allocated to said plurality of instructions independent of a number of said plurality of instructions; a future file configured to store a reorder buffer tag corresponding to a particular instruction, wherein said particular instruction is last, in program order, of the instructions represented within said instruction storage having a particular register as a destination operand, and wherein said future file is further configured to store a particular instruction result corresponding to said particular instruction when said particular instruction result is provided; and a control unit coupled to said instruction storage and to said future file, wherein said control unit is configured to allocate said first line of storage for said plurality of instructions, and wherein said control unit is further configured to update said future file if at least one of said plurality of instructions has said particular register as a destination operand; and an input/output (I/O) device coupled to said microprocessor said I/O device configured to communicate between said computer system and another computer system to which said I/O device is coupled.
Claim 21
Dependent Claim
15 words
The computer system as recited in claim 16 wherein said I/O device comprises a modem.
Claim 22
Dependent Claim
13 words
The computer system as recited in claim 15 further comprising a second microprocessor.
References Cited (Backward Citations)
US4044338A
Cited
US4453212A
Cited
US4928223A
Cited
US4807115A
Cited
US4858105A
Cited
EP0259095A2
Cited
EP0381471A2
Cited
US5226126A
Cited
US5136697A
Cited
US5129067A
Cited
US5226130A
Cited
US5058048A
Cited
US5053631A
Cited
EP0459232A2
Cited
US5197132A
Cited
US5355457A
Cited
US5689720A
Cited
US5560032A
Cited
US5345569A
Cited
GB2263987A
Cited
GB2263985A
Cited
WO1993020505A2
Cited
US5737624A
Cited
GB2281422A
Cited
US5446912A
Cited
US5548776A
Cited
US5574935A
Cited
US5524263A
Cited
US5584038A
Cited
US5623628A
Cited
EP0679991A1
Cited
US5632023A
Cited
US5535346A
Cited
EP0724213A2
Cited
WO1997013201A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |