Superscalar processor with a multi-port reorder buffer

Claim 1

A microprocessor comprising: an instruction fetch circuit for fetching instructions; an instruction decoder for decoding and issuing said instructions fetched; a superscalar execution cluster comprising a plurality of execution units for executing said instructions; out-of-order dispatch logic for dispatching said instructions issued to said plurality of execution units in said superscaler execution cluster; a reorder buffer coupled to said out-of-order dispatch logic for storing entries, including source data, corresponding to said instructions issued, said reorder buffer comprising: a plurality of write ports wherein each write port is coupled to an execution unit in said superscalar execution cluster, said plurality of write ports receiving data generated by said superscalar execution unit corresponding to said instructions executed in said superscalar execution unit, said plurality of write ports comprising: a write enable line; a write data line: a write transistor stack including: a first write transistor being controlled by said write data line and being coupled to ground such that a first state applied to said write data line results in conduction of current in said first write transistor to ground; a second write transistor coupling said first write transistor to said cell and being controlled by said write enable line such that when said second write transistor is enabled a conductive path is formed from said cell to ground: a third write transistor coupling said cell to said write data line and being controlled by said write enable line such that when said third write transistor is enabled a second state applied to said write data line drives said cell to said second state; and a plurality of read ports coupled to said superscalar execution unit and to said out-of order dispatch logic, said out-of-order dispatch logic utilizing two read ports to transfer said source data to one of said execution units in said superscalar execution cluster, said plurality of read ports comprising: a read enable line; a read data line; a precharge circuit for charging said read data line to a predetermined voltage level: a read transistor stack including: a first read transistor being controlled by said cell and being coupled to ground such that a second logic state stored in said cell results in conduction of current in said first read transistor; a second read transistor coupling said first read transistor to said read data line and being controlled by said read enable line such that when said second read transistor is enabled said second read transistor provides a conductive path from said read data line to said first read transistor, said first read transistor pulling said read data line to ground when said second state is stored in said cell, said read data line retaining said state when said first state is stored in said cell.