EP0724213A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method and system for reducing dispatch latency in a processor
Assignee: International Business Machines Corp
•
Filing: 1995-12-20
•
Granted: —
•
Expires: 2015-12-20
Abstract
Abstract A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.
Inventors
- 👤 Timothy Alan Elliot
- 👤 Christopher Hans Olson
- 👤 John Stephen Muhich
- 👤 Terence Matthew Potter
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 04:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/22; G06F9/3836; G06F9/3853
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
82 words
A method for reducing the dispatch latency of instructions of a processor, the processor including a cache receiving the instructions and a plurality of execution units for receiving the instructions from the cache; the method comprising the steps of: (a) reordering the instructions in a predetermined format before the instructions enter the cache; (b) storing information in the cache relating to the reordering of the instructions; and (c) providing the reordered instructions to the appropriate execution units based upon the predetermined format.
Claim 2
Dependent Claim
18 words
The method of claim 1 in which the instructions comprise branch, load, floating point and fixed point instructions.
Claim 3
Dependent Claim
23 words
The method of claim 2 in which the instructions are placed in each line of the cache in a left to right order.
Claim 4
Dependent Claim
39 words
The method of claim 2 in which the predetermined format comprises placing a first branch line in a left mast position in the cache line, and a first load instruction in a right most position in the cache line.
Claim 5
Dependent Claim
156 words
The method of claim 2 in which the reordering step (a) further comprises: (a1) inputting the instructions; (a2) determining if a next instruction is a branch instruction; if the instruction is a branch instruction; (a3) placing the instruction in the next branch instruction position; then return to step a1; if the next instruction is not a branch instruction; (a4) determining if the next instruction is a load instruction; if the next instruction is a load instruction; (a5) placing the instruction in the next load instruction position; then return to step (a1) if the next instruction is not a load instruction; (a6) determining if the next instruction is a floating point instruction; if the next instruction is a floating point instruction; (a7) placing the instruction in the next floating point instruction position; if the next instruction is not a floating point instruction; and (a8) placing the next instruction in a next available position of the cache line.
Claim 6
Dependent Claim
44 words
The method of claim 2 in which the reordering step further comprises: (a1) finding the first branch instruction and first load instruction and the first instruction; (a2) placing the first, first branch and first load instructions in the appropriate positions in the cache line.
Claim 7
Independent Claim
59 words
A system for reducing the dispatch latency in a processor comprising: a predispatch unit for receiving the instructions in a predetermined format and for providing reordering information; a cache memory for receiving the reordering information and the reordering instructions from the predispatch unit; and a plurality of execution units for receiving the reordered instructions based upon the predetermined format.
Claim 8
Dependent Claim
18 words
The system of claim 7 in which the instructions comprise branch, load, floating point and fixed point instructions.
Claim 9
Dependent Claim
23 words
The system of claim 8 in which the instructions are placed in each line of the cache in a left to right order.
Claim 10
Dependent Claim
39 words
The system of claim 8 in which the predetermined format comprises placing a first branch line in a left most position in the cache line, and a first load instruction in a right most position in the cache line.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.