Patent US5946571A successfully refreshed from Google Patents.
US5946571A
Expired / Lapsed
US
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Method of forming a capacitor
Assignee: United Microelectronics Corp
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Filing: 1997-11-21
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Granted: 1999-08-31
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Expires: 2017-11-21
Abstract
Abstract A DRAM capacitor is formed having a crown structure with a reduced number of processing steps. A planarized insulating layer is provided over the DRAM cell's transfer FET and a contact via is opened to one of the source/drain regions of the transfer FET. A layer of polysilicon is deposited to fill the contact via and to extend over the surface of the insulating layer, providing a thick polysilicon layer on the insulating layer. Conventional photolithography is used to define a first etching mask with an element on the thick polysilicon aligned over the contact via. The polysilicon layer is etched partially through using the first etching mask and the photoresist mask is removed. A layer of oxide is deposited over the elevated and recessed surfaces of the polysilicon layer and an etch back process is performed to form a second etching mask consisting of oxide spacer structures along the edges of the elevated portion of the polysilicon layer. Etching of the polysilicon layer is performed using the second etching mask, with the etch step proceeding completely through the recessed portions of the polysilicon layer and partially through the elevated portion of the polysilicon layer. The second etch mask is removed and a capacitor dielectric and an upper electrode are provided to complete formation of the charge storage capacitor for the DRAM cell.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Sun-Chieh Chien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:25
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
256 words
A method of making an integrated circuit device, comprising: providing a transfer FET having a first source/drain region formed in a substrate; forming an insulating layer over the transfer FET; forming a contact via through the insulating layer to expose at least a portion of the first source/drain region; providing a conductive interconnect within the contact via; providing a layer of conductive material over the insulating layer and connected to the first source/drain region through the conductive interconnect; providing a first etch mask over the layer of conductive material; etching partially through the layer of conductive material using the first etch mask to define an elevated portion of the layer of conductive material, the elevated portion of the layer of conductive material having edges aligned with the first etch mask and extending above a recessed position of the layer of conductive material by a first distance; removing the first etch mask and forming a second etch mask adjacent the edges of the elevated portion of the layer of conductive material, the second etch mask leaving exposed a surface of the elevated position of the layer of conductive material; forming at least a lower electrode of a charge storage structure by simultaneously etching partially through the elevated portion of the layer of conductive material and completely through the recessed portion of the layer of conductive material, using the second etch mask to define a peripheral portion of the lower electrode; providing a dielectric layer over the lower electrode; and providing an upper electrode over the dielectric layer.
Claim 2
Independent Claim
256 words
A method of making an integrated circuit device, comprising: providing a transfer FET having a first source/drain region formed in a substrate; forming an insulating layer over the transfer FET; forming a contact via through the insulating layer to expose at least a portion of the first source/drain region; providing a conductive interconnect within the contact via; providing a layer of conductive material over the insulating layer and connected to the first source/drain region through the conductive interconnect; providing a first etch mask over the layer of conductive material; etching partially through the layer of conductive material using the first etch mask to define an elevated portion of the layer of conductive material, the elevated portion of the layer of conductive material having edges aligned with the first etch mask and extending above a recessed position of the layer of conductive material by a first distance; removing the first etch mask and forming a second etch mask adjacent the edges of the elevated portion of the layer of conductive material, the second etch mask leaving exposed a surface of the elevated position of the layer of conductive material; forming at least a lower electrode of a charge storage structure by simultaneously etching partially through the elevated portion of the layer of conductive material and completely through the recessed portion of the layer of conductive material, using the second etch mask to define a peripheral portion of the lower electrode; providing a dielectric layer over the lower electrode; and providing an upper electrode over the dielectric layer.
Claim 3
Dependent Claim
20 words
The method of claim 1, further comprising the step of planarizing the insulating layer prior to forming the contact via.
Claim 4
Dependent Claim
23 words
The method of claim 2, wherein the layer of conductive material is doped polysilicon and wherein the layer of conductive material is planarized.
Claim 5
Dependent Claim
16 words
The method of claim 1, wherein the second etch mask is formed without a lithography process.
Claim 6
Dependent Claim
78 words
The method of claim 1, wherein the second etch mask is formed using the steps of: blanket depositing an etch material over the elevated portion of the layer of conductive material; and etching back the etch material to form the second etch mask so that the second etch mask extends along the edges of the elevated portion of the layer of conductive material and extends over a portion of the recessed portion of the layer of conductive material.
Claim 7
Dependent Claim
26 words
The method of claim 5, wherein the second etch mask does not extend onto the surface of the elevated portion of the layer of conductive material.
Claim 8
Dependent Claim
12 words
The method of claim 6, wherein the etch material is an oxide.
Claim 9
Dependent Claim
35 words
The method of claim 1, wherein the lower electrode includes a lower plate and a crown structure extending above the lower plate, the lower plate having a plate thickness approximately equal to the first distance.
Claim 10
Dependent Claim
30 words
The method of claim 2, further comprising the step of providing an etch stop layer over the insulating layer prior to the step of providing the layer of conductive material.
Claim 11
Dependent Claim
13 words
The method of claim 9, wherein the etch stop layer comprises silicon nitride.
Claim 12
Dependent Claim
29 words
The method of claim 9, wherein the etch stop layer provides a stop for the step of etching completely through the recessed portion of the layer of conductive material.
Claim 13
Dependent Claim
14 words
The method of claim 11, wherein the layer of conductive material is doped polysilicon.
Claim 14
Dependent Claim
38 words
The method of claim 1, wherein the lower electrode includes a lower plate and a crown structure extending above the lower plate, wherein the method further comprises the step of forming hemispherical grained silicon on the crown structure.
Claim 15
Dependent Claim
16 words
The method of claim 13, further comprising the step of etching back the hemispherical grained silicon.
Claim 16
Dependent Claim
40 words
The method of claim 1, wherein the elevated portion of the layer of conductive material is aligned over the contact via with the edges of the elevated portion aligned over the insulating layer subsequent to said forming a contact via.
References Cited (Backward Citations)
US4818715A
Cited
US4963504A
Cited
US5340763A
Cited
US5622889A
Cited
US5721153A
Cited
US5733808A
Cited
US5691229A
Cited
US5759895A
Cited
US5824592A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |