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US5824592A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming a stacked capacitor of a DRAM cell

Assignee: Vanguard International Semiconductor Corp
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Filing: 1997-12-03
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Granted: 1998-10-20
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Expires: 2017-12-03
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Abstract

Abstract A method for forming a capacitor of a dynamic random access memory cell is disclosed. The method includes forming a polysilicon layer (124) over a semiconductor layer, wherein at least a portion of the polysilicon layer is communicated to the substrate, and then patterning to etch a portion of the polysilicon layer. A mask layer (126) is formed on a portion of the polysilicon layer, and at least one silicon oxide region (128A) is formed in the polysilicon not covered by the mask layer. After etching a portion of the polysilicon layer using the silicon oxide region as an etch mask, a capacitor dielectric layer (136) is formed on the polysilicon layer, and a conductive layer (138) is formed on the capacitor dielectric layer.

Inventors

  • 👤 Horng-Huei Tseng

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 14:30
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 178 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a first dielectric layer on a semiconductor substrate; patterning said first dielectric layer to form a node contact in said first dielectric layer, thereby exposing a portion of the substrate; forming a polysilicon layer on said first dielectric layer, said polysilicon layer filling the node contact in said first dielectric layer; forming a photoresist layer on said polysilicon layer; etching said polysilicon layer using said photoresist layer as a mask; laterally eroding a portion of said photoresist layer; implanting oxygen atoms into said polysilicon layer using said eroded photoresist layer as a mask, thereby forming at least one oxygen region in said polysilicon layer; annealing said polysilicon layer to convert said at least one oxygen region into at least one silicon oxide region; etching a portion of said polysilicon layer using said at least one silicon oxide region as an etch mask; forming a second dielectric layer on said polysilicon layer; and forming a conductive layer on said second dielectric layer.
Claim 2
Independent Claim 178 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a first dielectric layer on a semiconductor substrate; patterning said first dielectric layer to form a node contact in said first dielectric layer, thereby exposing a portion of the substrate; forming a polysilicon layer on said first dielectric layer, said polysilicon layer filling the node contact in said first dielectric layer; forming a photoresist layer on said polysilicon layer; etching said polysilicon layer using said photoresist layer as a mask; laterally eroding a portion of said photoresist layer; implanting oxygen atoms into said polysilicon layer using said eroded photoresist layer as a mask, thereby forming at least one oxygen region in said polysilicon layer; annealing said polysilicon layer to convert said at least one oxygen region into at least one silicon oxide region; etching a portion of said polysilicon layer using said at least one silicon oxide region as an etch mask; forming a second dielectric layer on said polysilicon layer; and forming a conductive layer on said second dielectric layer.
Claim 3
Dependent Claim 23 words
The method according to claim 1, before forming said first dielectric layer, further comprising conformably forming a thin dielectric layer on the substrate.
Claim 4
Dependent Claim 15 words
The method according to claim 1, wherein said first dielectric layer comprises doped silicon oxide.
Claim 5
Dependent Claim 15 words
The method according to claim 1, wherein said polysilicon layer is annealed in a furnace.
Claim 6
Dependent Claim 17 words
The method according to claim 1, wherein said polysilicon layer is annealed by a rapid thermal process.

References Cited (Backward Citations)

US5429980A Cited
US5656532A Cited
US5723373A Cited
US5670406A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-10-19 2002-04-20 2002-10-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-10-19 2006-04-20 2006-10-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-10-19 2010-04-20 2010-10-20 $7700.00 Window Closed / Lapsed

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