Abstract A method for forming a capacitor of a dynamic random access memory cell is disclosed. The method includes forming a polysilicon layer (124) over a semiconductor layer, wherein at least a portion of the polysilicon layer is communicated to the substrate, and then patterning to etch a portion of the polysilicon layer. A mask layer (126) is formed on a portion of the polysilicon layer, and at least one silicon oxide region (128A) is formed in the polysilicon not covered by the mask layer. After etching a portion of the polysilicon layer using the silicon oxide region as an etch mask, a capacitor dielectric layer (136) is formed on the polysilicon layer, and a conductive layer (138) is formed on the capacitor dielectric layer.
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a first dielectric layer on a semiconductor substrate; patterning said first dielectric layer to form a node contact in said first dielectric layer, thereby exposing a portion of the substrate; forming a polysilicon layer on said first dielectric layer, said polysilicon layer filling the node contact in said first dielectric layer; forming a photoresist layer on said polysilicon layer; etching said polysilicon layer using said photoresist layer as a mask; laterally eroding a portion of said photoresist layer; implanting oxygen atoms into said polysilicon layer using said eroded photoresist layer as a mask, thereby forming at least one oxygen region in said polysilicon layer; annealing said polysilicon layer to convert said at least one oxygen region into at least one silicon oxide region; etching a portion of said polysilicon layer using said at least one silicon oxide region as an etch mask; forming a second dielectric layer on said polysilicon layer; and forming a conductive layer on said second dielectric layer.
Claim 2
Independent Claim
178 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a first dielectric layer on a semiconductor substrate; patterning said first dielectric layer to form a node contact in said first dielectric layer, thereby exposing a portion of the substrate; forming a polysilicon layer on said first dielectric layer, said polysilicon layer filling the node contact in said first dielectric layer; forming a photoresist layer on said polysilicon layer; etching said polysilicon layer using said photoresist layer as a mask; laterally eroding a portion of said photoresist layer; implanting oxygen atoms into said polysilicon layer using said eroded photoresist layer as a mask, thereby forming at least one oxygen region in said polysilicon layer; annealing said polysilicon layer to convert said at least one oxygen region into at least one silicon oxide region; etching a portion of said polysilicon layer using said at least one silicon oxide region as an etch mask; forming a second dielectric layer on said polysilicon layer; and forming a conductive layer on said second dielectric layer.
Claim 3
Dependent Claim
23 words
The method according to claim 1, before forming said first dielectric layer, further comprising conformably forming a thin dielectric layer on the substrate.
Claim 4
Dependent Claim
15 words
The method according to claim 1, wherein said first dielectric layer comprises doped silicon oxide.
Claim 5
Dependent Claim
15 words
The method according to claim 1, wherein said polysilicon layer is annealed in a furnace.
Claim 6
Dependent Claim
17 words
The method according to claim 1, wherein said polysilicon layer is annealed by a rapid thermal process.