Patent US5945707A successfully refreshed from Google Patents.
US5945707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DRAM cell with grooved transfer device
Assignee: Cavium International
•
Filing: 1998-04-07
•
Granted: 1999-08-31
•
Expires: 2018-04-07
Abstract
Abstract A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.
Inventors
- 👤 Gary B. Bronner
- 👤 Toshiharu Furukawa
- 👤 Mark C. Hakey
- 👤 Steven J. Holmes
- 👤 David V. Horak
- 👤 Jack A. Mandelman
- 👤 Paul A. Rabidoux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:14
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/05; H10B12/053; H10B12/30; H10B12/48; H10B12/488; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0151; H10D84/80; H10D84/82; H10D84/83; H10D84/834
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
109 words
A semiconductor device comprising: first and second regions of a first conductivity type formed in a substrate of a second conductivity type; and a grooved gate formed in a groove located in said substrate between said first and second regions; said grooved gate having sidewall portions and a bottom portion, and defining a channel located in said substrate along said gate sidewall and bottom portions; sidewall sections of said channel located along said gate sidewall portion having a larger length than a bottom length of a bottom section of said channel located along said gate bottom portion so that said gate sidewall portions of said channel control said device.
Claim 2
Dependent Claim
109 words
A semiconductor device comprising: first and second regions of a first conductivity type formed in a substrate of a second conductivity type; and a grooved gate formed in a groove located in said substrate between said first and second regions; said grooved gate having sidewall portions and a bottom portion, and defining a channel located in said substrate along said gate sidewall and bottom portions; sidewall sections of said channel located along said gate sidewall portion having a larger length than a bottom length of a bottom section of said channel located along said gate bottom portion so that said gate sidewall portions of said channel control said device.
Claim 3
Dependent Claim
35 words
The semiconductor device of claim 1 further comprising an isolation region formed in said substrate to isolate said semiconductor device; said isolation region having a depth which is greater than a depth of said groove.
Claim 4
Dependent Claim
34 words
The semiconductor device of claim 1 further comprising a deep trench capacitor formed in said substrate, said deep trench capacitor having a storage electrode electrically connected to one of said first and second regions.
Claim 5
Dependent Claim
19 words
The semiconductor device of claim 1 further comprising a doped well region located between said substrate and said groove.
Claim 6
Dependent Claim
21 words
The semiconductor device of claim 1, wherein said gate sidewall portions control said semiconductor device more than said gate bottom portions.
Claim 7
Dependent Claim
34 words
The semiconductor device of claim 1, wherein one of said channel sidewall sections located along one of said gate sidewall portions has a larger length than said bottom length of said bottom channel section.
Claim 8
Dependent Claim
19 words
The semiconductor device of claim 1, wherein a length of said groove approximately equals a width of said channel.
Claim 9
Dependent Claim
23 words
The semiconductor device of claim 1, wherein a length of said channel includes a width of said groove along said gate bottom portion.
Claim 10
Dependent Claim
21 words
The semiconductor device of claim 1, wherein a length of said channel includes a depth and a width of said groove.
Claim 11
Dependent Claim
41 words
The semiconductor device of claim 1, wherein said first and second regions are separated from said groove by top lateral sections of said channel, and said grooved gate extends over said top lateral channel sections to said first and second regions.
Claim 12
Dependent Claim
35 words
The semiconductor device of claim 10, wherein said extended grooved gate extends a length of said channel to include distances of said top lateral channel sections, said channel sidewall sections and said channel bottom section.
Claim 13
Dependent Claim
39 words
The semiconductor device of claim 1, wherein said groove is a stepped groove and said grooved gate is a stepped grooved gate; each of said gate sidewalls being separated by a lateral step into top and bottom sidewall parts.
Claim 14
Dependent Claim
32 words
The semiconductor device of claim 12, wherein an upper width of said groove between said top sidewall parts is larger than a lower width of said groove between said bottom sidewall parts.
Claim 15
Dependent Claim
17 words
The semiconductor device of claim 1, wherein said groove is centered between said first and second regions.
Claim 16
Dependent Claim
19 words
The semiconductor device of claim 1, wherein said first and second regions are self aligned to said grooved gate.
References Cited (Backward Citations)
US4003126A
Cited
US4048649A
Cited
US4243997A
Cited
US4296429A
Cited
US4191963A
Cited
US4455740A
Cited
US4453305A
Cited
US4571815A
Cited
FR2526586A1
Cited
US4499651A
Cited
US5640034A
Cited
US5726463A
Cited
US5408116A
Cited
US5583065A
Cited
US5623152A
Cited
US5614431A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |