Method of making buried strap trench cell yielding an extended transistor

Abstract

Abstract A process sequence, cell structure, and cell layout for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The process sequence may allow elimination of deep trench collar or cap deposition, or reduction of word line to word line capacitance. The cell prepared by the method allows a two lithographic feature transfer device channel length in an eight square folded bit line DRAM cell. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The cell requires only one additional mask (GPC) and minimal additional processing. The process sequence starts with deep trench (DT) processing, followed by deposition of SiO 2 , planarization and pad strip. Then gate SiO 2 , polysilicon, and pad are deposited. The structure is etched using a shallow trench isolation mask and filled with SiO 2 . After planarization, a thin insulator is deposited and the structure is etched again with a Gate Poly Contact mask. A gate conductor is then deposited. After a final etch, wiring is added.

Inventors

• 👤 John K. DeBrosse

Bibliographic Details