Method of making vertical channel field controlled device employing a recessed gate structure

Claim 1

A method of fabricating a vertical channel electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising: providing a semiconductor wafer having a base layer of the one conductivity type; forming a layer of silicon dioxide with a plurality of windows on one surface of the base layer, alternate windows defining the ultimate locations of upper electrode regions and gate regions; forming an etchant barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of gate regions, and to leave open the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions; introducing into the base layer through the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions impurities appropriate to form upper electrode regions of the one conductivity type and of higher conductivity than the base region; growing an oxide layer over the diffused upper electrode regions thinner than the oxide layer over the remainder of the base layer; removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of gate regions; forming substantially vertically-walled grooves beneath the gate region windows; introducing into the sidewalls and bottoms of the grooves impurities appropriate to form gate regions of the opposite conductivity type; removing the oxide layer over the upper electrode regions; and evaporating metal onto the wafer surface to form metalized source terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

Claim 2

A method of fabricating a vertical channel electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising: providing a semiconductor wafer having a base layer of the one conductivity type; forming a layer of silicon dioxide with a plurality of windows on one surface of the base layer, alternate windows defining the ultimate locations of upper electrode regions and gate regions; forming an etchant barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of gate regions, and to leave open the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions; introducing into the base layer through the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions impurities appropriate to form upper electrode regions of the one conductivity type and of higher conductivity than the base region; growing an oxide layer over the diffused upper electrode regions thinner than the oxide layer over the remainder of the base layer; removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of gate regions; forming substantially vertically-walled grooves beneath the gate region windows; introducing into the sidewalls and bottoms of the grooves impurities appropriate to form gate regions of the opposite conductivity type; removing the oxide layer over the upper electrode regions; and evaporating metal onto the wafer surface to form metalized source terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

Claim 6

A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising: providing a semiconductor wafer having a base layer of the one conductivity type, and of crystallographic orientation selected to facilitate preferential etching; forming a layer of silicon dioxide with a plurality of elongated windows on one surface of the base layer, alternate windows defining the ultimate locations of upper electrode regions and gate regions; forming a barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of gate regions, and to leave open the windows in the silicon dioxide layer defining the ultimate locations of the upper electrode regions; introducing into the base layer through the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions impurities appropriate to form electrode regions of the one conductivity type and of higher conductivity than the base region; growing an oxide layer over the diffused electrode regions thinner than the oxide layer over the remainder of the base layer; removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of the gate regions; preferentially etching the base layer to form substantially vertically-walled grooves beneath the gate region windows with undercutting of the oxide layer surrounding the gate region windows; introducing into the sidewalls and bottoms of the grooves impurities appropriate to form gate regions of the opposite conductivity type; removing the oxide layer over the upper electrode regions; and evaporating metal onto the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

Claim 7

A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising: providing a semiconductor wafer having a base layer of the one conductivity type, and of crystallographic orientation selected to facilitate preferential etching; forming a layer of silicon dioxide with a plurality of elongated windows on one surface of the base layer, alternate windows defining the ultimate locations of upper electrode regions and gate regions; forming a barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of gate regions, and to leave open the windows in the silicon dioxide layer defining the ultimate locations of the upper electrode regions; introducing into the base layer through the windows in the silicon dioxide layer defining the ultimate locations of upper electrode regions impurities appropriate to form electrode regions of the one conductivity type and of higher conductivity than the base region; growing an oxide layer over the diffused electrode regions thinner than the oxide layer over the remainder of the base layer; removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of the gate regions; preferentially etching the base layer to form substantially vertically-walled grooves beneath the gate region windows with undercutting of the oxide layer surrounding the gate region windows; introducing into the sidewalls and bottoms of the grooves impurities appropriate to form gate regions of the opposite conductivity type; removing the oxide layer over the upper electrode regions; and evaporating metal onto the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.