Patent US5943490A successfully refreshed from Google Patents.
US5943490A
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Distributed logic analyzer for use in a hardware logic emulation system
Assignee: Cadence Design Systems Inc
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Filing: 1997-05-30
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Granted: 1999-08-24
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Expires: 2017-05-30
Abstract
Abstract A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
Inventors
- 👤 Stephen P. Sample
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:31
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G01R31/3181; G01R31/3185; G06F11/00; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
190 words
A logic analyzer integrated in a hardware logic emulation system that emulates a logic design, the logic emulation system comprising a plurality of logic chips, the plurality of logic chips being interconnected to each other by a plurality of interconnect chips, the logic design comprising combinational logic elements and sequential logic elements, the logic analyzer comprising: at least one scan chain programmed into each of said plurality of logic chips, said at least one scan chain comprised of a flip-flop, said at least one scan chain programmably connectable to outputs of a selected subset of the sequential logic elements of the logic design; at least one memory device, said at least one memory device in communication with said at least one scan chain and storing data from the sequential logic elements of the logic design; and control circuitry, said control circuitry in communication with said plurality of logic chips, said control circuitry generating logic analyzer clock signals and trigger signals, said logic analyzer clock signals clocking said at least one scan chain, said trigger signals being generated when a predetermined combination of signals occur in said plurality of logic chips.
Claim 2
Dependent Claim
190 words
A logic analyzer integrated in a hardware logic emulation system that emulates a logic design, the logic emulation system comprising a plurality of logic chips, the plurality of logic chips being interconnected to each other by a plurality of interconnect chips, the logic design comprising combinational logic elements and sequential logic elements, the logic analyzer comprising: at least one scan chain programmed into each of said plurality of logic chips, said at least one scan chain comprised of a flip-flop, said at least one scan chain programmably connectable to outputs of a selected subset of the sequential logic elements of the logic design; at least one memory device, said at least one memory device in communication with said at least one scan chain and storing data from the sequential logic elements of the logic design; and control circuitry, said control circuitry in communication with said plurality of logic chips, said control circuitry generating logic analyzer clock signals and trigger signals, said logic analyzer clock signals clocking said at least one scan chain, said trigger signals being generated when a predetermined combination of signals occur in said plurality of logic chips.
Claim 3
Dependent Claim
32 words
The logic analyzer of claim 1 further comprising a means for calculating states of the combinational logic elements in the logic design from data stored in said at least one memory device.
Claim 4
Dependent Claim
19 words
The logic analyzer of claim 1 wherein each of said plurality of logic chips comprise field programmable gate arrays.
Claim 5
Dependent Claim
25 words
The logic analyzer of claim 3 wherein said at least one scan chain is programmed into configurable logic cells within said field programmable gate arrays.
Claim 6
Dependent Claim
41 words
The logic analyzer of claim 4 wherein said at least one scan chain is programmably connected to outputs of said selected subset of the sequential logic elements of the logic design using configurable routing resources within said field programmable gate arrays.
Claim 7
Dependent Claim
28 words
The logic analyzer of claim 1 wherein said at least one memory device communicates with said at least one scan chain through the plurality of programmable interconnect chips.
Claim 8
Dependent Claim
22 words
The logic analyzer of claim 1 wherein said logic chips have event logic implemented therein which computes said predetermined combination of signals.
Claim 9
Dependent Claim
26 words
The logic analyzer of claim 3 wherein the plurality of field programmable gate arrays has event logic programmed therein which computes said predetermined combination of signals.
Claim 10
Dependent Claim
185 words
A logic analyzer integrated in a hardware logic emulation system that emulates a logic design, the logic emulation system comprising a plurality of logic chips, the plurality of logic chips being programmably interconnected to each other, the logic design comprising combinational logic elements and sequential logic elements, the logic analyzer comprising: at least one scan chain programmed into each of said plurality of logic chips, said at least one scan chain comprised of a flip-flop, said at least one scan chain programmably connectable to outputs of a selected subset of the sequential logic elements of the logic design; at least one memory device, said at least one memory device in communication with said at least one scan chain and storing data from the sequential logic elements of the logic design; and control circuitry, said control circuitry in communication with said plurality of logic chips, said control circuitry generating logic analyzer clock signals and trigger signals, said logic analyzer clock signals clocking said at least one scan chain, said trigger signals being generated when a predetermined combination of signals occur in said plurality of logic chips.
Claim 11
Dependent Claim
185 words
A logic analyzer integrated in a hardware logic emulation system that emulates a logic design, the logic emulation system comprising a plurality of logic chips, the plurality of logic chips being programmably interconnected to each other, the logic design comprising combinational logic elements and sequential logic elements, the logic analyzer comprising: at least one scan chain programmed into each of said plurality of logic chips, said at least one scan chain comprised of a flip-flop, said at least one scan chain programmably connectable to outputs of a selected subset of the sequential logic elements of the logic design; at least one memory device, said at least one memory device in communication with said at least one scan chain and storing data from the sequential logic elements of the logic design; and control circuitry, said control circuitry in communication with said plurality of logic chips, said control circuitry generating logic analyzer clock signals and trigger signals, said logic analyzer clock signals clocking said at least one scan chain, said trigger signals being generated when a predetermined combination of signals occur in said plurality of logic chips.
Claim 12
Dependent Claim
32 words
The logic analyzer of claim 9 further comprising a means for calculating states of the combinational logic elements in the logic design from data stored in said at least one memory device.
Claim 13
Dependent Claim
19 words
The logic analyzer of claim 9 wherein each of said plurality of logic chips comprise field programmable gate arrays.
Claim 14
Dependent Claim
25 words
The logic analyzer of claim 11 wherein said at least one scan chain is programmed into configurable logic cells within said field programmable gate arrays.
Claim 15
Dependent Claim
41 words
The logic analyzer of claim 12 wherein said at least one scan chain is programmably connected to outputs of said selected subset of the sequential logic elements of the logic design using configurable routing resources within said field programmable gate arrays.
Claim 16
Dependent Claim
22 words
The logic analyzer of claim 9 wherein said logic chips have event logic implemented therein which computes said predetermined combination of signals.
Claim 17
Dependent Claim
26 words
The logic analyzer of claim 11 wherein the plurality of field programmable gate arrays has event logic programmed therein which computes said predetermined combination of signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |