US5659716A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
Assignee: Mentor Graphics Corp
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Filing: 1994-11-23
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Granted: 1997-08-19
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Expires: 2014-11-23
Abstract
Abstract A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously. Previously, the calculations and communications were divided into discrete phases within each emulation clock period.
Inventors
- 👤 Charles W. Selvidge
- 👤 Anant Agarwal
- 👤 Johnathan Babb
- 👤 Matthew L. Dahl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:02
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
136 words
A configurable logic system programmed to model a logic design, the system comprising an array of programmable logic modules each configured to perform a partition block of the logic design, and a module interconnect for each programmable logic module providing connections between the modules of the array enabling transmission of global links between the partition blocks of the modules, at least one of the modules time division multiplexing the global links transmitted over the interconnect to another one of the modules, which demultiplexes the global links, the modules being configured to transmit individual ones of the global links over the module interconnect at scheduled time intervals determined in response to ready times of the individual links and the modules being configured to receive the global links from the module interconnect based on the scheduled time intervals.
Claim 2
Dependent Claim
136 words
A configurable logic system programmed to model a logic design, the system comprising an array of programmable logic modules each configured to perform a partition block of the logic design, and a module interconnect for each programmable logic module providing connections between the modules of the array enabling transmission of global links between the partition blocks of the modules, at least one of the modules time division multiplexing the global links transmitted over the interconnect to another one of the modules, which demultiplexes the global links, the modules being configured to transmit individual ones of the global links over the module interconnect at scheduled time intervals determined in response to ready times of the individual links and the modules being configured to receive the global links from the module interconnect based on the scheduled time intervals.
Claim 3
Dependent Claim
36 words
A configurable logic system as claimed in claim 1, wherein the ready times of individual global links are determined in response to receipt of parent global links affecting a logic value of the individual global links.
Claim 4
Dependent Claim
36 words
A configurable logic system as claimed in claim 2, wherein the ready times of individual global links are further determined in response to propagation delays for combinatorial signals across partition blocks generating the individual global links.
Claim 5
Dependent Claim
54 words
A configurable logic system as claimed in claim 1, wherein the modules comprise: logic partition portions configured to logically model a corresponding partition block by generating the corresponding global links; and communication portions configured to time multiplex the global links generated by the logic partition portions for transmission over the interconnect between the modules.
Claim 6
Dependent Claim
31 words
A configurable logic system as claimed in claim 4, further comprising a pipeline clock received by the communication portions of the modules for defining time blocks for multiplexing the global links.
Claim 7
Dependent Claim
34 words
A configurable logic system as claimed in claim 5, wherein the global links having long paths between programmable logic modules are routed through intermediate programmable logic modules between source and destination programmable logic modules.
Claim 8
Dependent Claim
30 words
A configurable logic system as claimed in claim 5, wherein the programmable logic modules buffer global links in flip-flops or registers until a path on the module interconnect becomes available.
Claim 9
Dependent Claim
17 words
A configurable logic system as claimed in claim 4, wherein the communication portions comprise pipeline shift registers.
Claim 10
Dependent Claim
15 words
A configurable logic system as claimed in claim 4, wherein the communication portions comprise multiplexers.
Claim 11
Dependent Claim
23 words
A configurable logic system as claimed in claim 9, wherein the communication portions further comprise flip flops at the inputs to the multiplexers.
Claim 12
Dependent Claim
22 words
A configurable logic system as claimed in claim 9, wherein the communication portions further comprise flip flops receiving outputs of the multiplexers.
Claim 13
Dependent Claim
44 words
A configurable logic system as claimed in claim 5, wherein the communications portions transmit individual global links over periods of the pipeline clock determined in response to a time of receipt of parent global links affecting a logic value of the individual global links.
Claim 14
Dependent Claim
44 words
A configurable logic system as claimed in claim 12, wherein the period of the pipeline clock over which individual global links are transmitted is further determined in response to propagation delays across the logic partition portions for combinatorial signals generating the individual global links.
Claim 15
Dependent Claim
17 words
A configurable logic system as claimed in claim 1, wherein the modules are field programmable gate arrays.
Claim 16
Independent Claim
68 words
A method for compiling a netlist comprising: dividing the netlist into a logic partition blocks to be loaded into programmable logic modules of an array; routing individual global links to be transmitted between the modules on an interconnect on time intervals defined by a clock signal; and determining the time intervals in response to receipt of parent global links affecting a logic value of the individual global links.
Claim 17
Independent Claim
68 words
A method for compiling a netlist comprising: dividing the netlist into a logic partition blocks to be loaded into programmable logic modules of an array; routing individual global links to be transmitted between the modules on an interconnect on time intervals defined by a clock signal; and determining the time intervals in response to receipt of parent global links affecting a logic value of the individual global links.
Claim 18
Dependent Claim
55 words
A compiling method as claimed in claim 15, further comprising: determining link depths of the global links, link depths referring to a number of other global links that must be routed after a given global link for correct operation; and assigning priority to the routing of the global links in response to the link depths.
Claim 19
Dependent Claim
43 words
A compiling method as claimed in claim 15, further comprising: separating the global links into virtually routable global links and hard routable global links; and routing only virtually routable global links to be transmitted between the modules in response to the clock signal.
Claim 20
Dependent Claim
29 words
A compiling method as claimed in claim 15, further comprising determining the time intervals in response to propagation delays across the logic partition blocks of the individual global links.
Claim 21
Dependent Claim
18 words
A compiling method as claimed in claim 16, wherein the time intervals are defined by a pipe-line clock.
Claim 22
Dependent Claim
31 words
A compiling method as claimed in claim 15, further comprising allocating multiple periods of the pipe-line clock for the propagation delays across the logic partition blocks of the individual global links.
Claim 23
Dependent Claim
31 words
A compiling method as claimed in claim 19, further comprising determining a period of the pipe-line clock in response to a maximum propagation delay between programmable logic modules of the array.
Claim 24
Dependent Claim
27 words
A compiling method as claimed in claim 15, further comprising routing the individual global links along one or more shortest paths between a source and destination module.
Claim 25
Dependent Claim
32 words
A compiling method as claimed in claim 15, further comprising routing global links having long paths between programmable logic modules through intermediate programmable logic modules between source and destination programmable logic modules.
Claim 26
Dependent Claim
106 words
A configurable logic system programmed to model a logic design, the system comprising: an array of programmable logic modules; a module interconnect providing connections between the modules of the array enabling transmission of global links between the modules; and a configurer for configuring each one of the modules to perform a partition block of the logic design and time division multiplex individual ones of the global links over the module interconnect at scheduled time intervals determined in response to ready times of the individual global links and the modules being configured to receive the global links from the module interconnect based on the scheduled time intervals.
Claim 27
Dependent Claim
106 words
A configurable logic system programmed to model a logic design, the system comprising: an array of programmable logic modules; a module interconnect providing connections between the modules of the array enabling transmission of global links between the modules; and a configurer for configuring each one of the modules to perform a partition block of the logic design and time division multiplex individual ones of the global links over the module interconnect at scheduled time intervals determined in response to ready times of the individual global links and the modules being configured to receive the global links from the module interconnect based on the scheduled time intervals.
Claim 28
Dependent Claim
36 words
A configurable logic system as claimed in claim 24, wherein the ready times of individual global links are determined in response to receipt of parent global links affecting a logic value of the individual global links.
Claim 29
Dependent Claim
36 words
A configurable logic system as claimed in claim 25, wherein the ready times of individual global links are further determined in response to propagation delays across partition blocks for combinatorial signals generating the individual global links.
Claim 30
Dependent Claim
54 words
A configurable logic system as claimed in claim 24, wherein the modules comprise: logic partition portions configured to logically model a corresponding partition block by generating the corresponding global links; and communication portions configured to time multiplex the global links generated by the logic partition portions for transmission over the interconnect between the modules.
Claim 31
Dependent Claim
17 words
A configurable logic system as claimed in claim 24, wherein the modules are field programmable gate arrays.
Claim 32
Dependent Claim
16 words
A configurable logic system as claimed in claim 24, wherein the configurer is a host workstation.
Claim 33
Dependent Claim
35 words
A configurable logic system as claimed in claim 24, wherein the configurer collectively configures the modules to transmit global links having long paths through intermediate programmable logic modules between source and destination programmable logic modules.
Claim 34
Dependent Claim
28 words
A configurable logic system as claimed in claim 24, wherein the configurer configures the modules to buffer global links until a path on the module interconnect becomes available.
Claim 35
Dependent Claim
17 words
A configurable logic system as claimed in claim 27, wherein the communication portions comprise pipeline shift registers.
Claim 36
Dependent Claim
15 words
A configurable logic system as claimed in claim 27, wherein the communication portions comprise multiplexers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-18 | 2001-02-17 | 2001-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-18 | 2005-02-17 | 2005-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-18 | 2009-02-17 | 2009-08-19 | $7700.00 | Window Closed / Lapsed |