Interlaced programmable logic array having shared elements

Claim 2

In a programmable logic array circuit including a first logic array responsive to first input signals for providing first output signals corresponding to the logical product terms of selected input signals during a first time interval and second logic array responsive to second input signals to provide during a second time interval output signals corresponding to sums of selected product terms provided by the first logic array, each logic array including a plurality of input lines and a plurality of output lines, the improvement characterized in that at least some of the input lines of both of the first and second logic arrays are physically common and at least some of the output lines of both the first and second logic arrays are physically common, said programmable logic array circuit including first logic means for providing logical representations of the logical product terms generated by the first logic array to the common input lines to generate a sum of product terms on the output lines during the second time interval.

Claim 3

The programmable logic array circuit of claim 1 wherein the first logic means includes a plurality of logical circuits coupled to selected ones of the output lines for performing a predetermined logic function on at least some of the first output signals during the first time interval and for performing the predetermined logic function on at least some of the second output signals provided on the same output lines during the second time interval.

Claim 4

The programmable logic array circuit of claim 2 wherein the predetermined logic function is that of the Exclusive-OR function.

Claim 5

The programmable logic array circuit of claim 2 wherein the first logic means comprises a plurality of Exclusive-NOR circuits.

Claim 6

The programmable logic array circuit of claim 1 wherein the first logic means includes first logical NOR circuitry for providing a first logical NOR function of at least one of the product term-containing signals for application to the input lines of the second logic array during the second time interval.

Claim 7

The programmable logic array circuit of claim 5 wherein the first logic means further includes second logical NOR circuitry for providing a second logical NOR function of the same product term-containing signals as the first logical NOR circuitry and at least one of a different one of the product term-containing signals.

Claim 8

The programmable logic array circuit of claim 1 wherein the first and second logic arrays comprise a plurality of NOR circuits.

Claim 9

A programmable logic array circuit for implementing the binary addition of a pair of n-bit binary numbers including a plurality of input decoders responsive to corresponding bits of said binary numbers for generating simple binary addition logical functions, a logical AND array responsive to said functions for generating a plurality of product terms and a logical OR array responsive to a plurality of input signals for generating a plurality of sum terms, the improvement comprising: a plurality of Exclusive-NOR circuit means for generating logical Exclusive-NOR functions in response to pairs of input signals; a plurality of NOR circuit means for generating logical NOR functions in response to input signals; first means for coupling selected pairs of product terms to the inputs of at least one Exclusive-NOR circuit means; second means for coupling the inputs of at least said one of said Exclusive-NOR circuit means to at least one of said NOR circuit means; third means for coupling selected paris of sum terms to at least one of said Exclusive-NOR circuit means; and fourth means for coupling the output of at least one of said Exclusive-NOR means to an output circuit, said output being representative of at least one of the output bits of the sum of the n-bit binary number to be added.

Claim 10

A programmable logic array circuit for implementing the binary addition of a pair of n-bit binary numbers including a plurality of input decoders responsive to corresponding bits of said binary numbers for generating simple binary addition logical functions, a logical AND array responsive to said functions for generating a plurality of product terms and a logical OR array responsive to a plurality of input signals for generating a plurality of sum terms, the improvement comprising: a plurality of Exclusive-NOR circuit means for generating logical Exclusive-NOR functions in response to pairs of input signals; a plurality of NOR circuit means for generating logical NOR functions in response to input signals; first means for coupling selected pairs of product terms to the inputs of at least one Exclusive-NOR circuit means; second means for coupling the inputs of at least said one of said Exclusive-NOR circuit means to at least one of said NOR circuit means; third means for coupling selected paris of sum terms to at least one of said Exclusive-NOR circuit means; and fourth means for coupling the output of at least one of said Exclusive-NOR means to an output circuit, said output being representative of at least one of the output bits of the sum of the n-bit binary number to be added.

Claim 11

The programmable logic array circuit of claim 8 wherein the selected pairs of product terms and sum terms are applied to at least one (some) of the same Exclusive-NOR circuits during two different time intervals, the output of which is provided to the NOR circuits during a first time interval and to output circuits during a second time interval.

Claim 12

The programmable logic array circuit of claim 9 wherein the AND and the OR array are implemented as logical NOR circuits.