EP0410502A2
Expired / Lapsed
EP
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Method and apparatus for emulating interaction between application specific integrated circuit (asic) under development and target system
Assignee: LSI Corp
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Filing: 1990-07-11
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Granted: —
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Expires: 2010-07-11
Abstract
Abstract An integrated circuit under development is tightly coupled to its target system such that the behaviors of the integrated circuit under development and the target system may be studied in real or pseudo-real time fashion. A pin dummy emulates the function of real pins on the yet-to-be-developed integrated circuit. A mirror relationship is established between cells of a real-pin register means and corresponding cells of virtual-pin nodes in the integrated circuit under development such that input signals presented at input ones of the real pins in the pin dummy are projected to input ones of virtual pins in the integrated circuit under development and further such that output levels of virtual-pins in the integrated circuit under development are projected to corresponding output ones of the real pins on the pin dummy.
Inventors
- 👤 Daniel R. Watkins
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:10
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
179 words
A method for developing an application specific integrated circuit which is to be inserted into a target system, where the target system has predetermined pin coupling points for coupling to physical pins of the to-be-developed integrated circuit, the method comprising: creating a software model of the to-be-developed integrated circuit; designating nodes within the software model as virtual pin nodes; designating predetermined ones of the virtual pin nodes as virtual input pin nodes and virtual output pin nodes; stepping the software model by a predetermined number of cycles to generate logic states at the virtual output pin nodes thereof; transmitting output signals representing the logic states of the virtual output pin nodes to corresponding input ones of the pin coupling points in the target system; stepping the target system by a predetermined number of cycles to generate logic states at preselected output ones of the pin coupling points in the target system; and transmitting input signals representing logic states of the preselected output pin coupling points of the target system to corresponding virtual input pin nodes of the software model.
Claim 2
Independent Claim
179 words
A method for developing an application specific integrated circuit which is to be inserted into a target system, where the target system has predetermined pin coupling points for coupling to physical pins of the to-be-developed integrated circuit, the method comprising: creating a software model of the to-be-developed integrated circuit; designating nodes within the software model as virtual pin nodes; designating predetermined ones of the virtual pin nodes as virtual input pin nodes and virtual output pin nodes; stepping the software model by a predetermined number of cycles to generate logic states at the virtual output pin nodes thereof; transmitting output signals representing the logic states of the virtual output pin nodes to corresponding input ones of the pin coupling points in the target system; stepping the target system by a predetermined number of cycles to generate logic states at preselected output ones of the pin coupling points in the target system; and transmitting input signals representing logic states of the preselected output pin coupling points of the target system to corresponding virtual input pin nodes of the software model.
Claim 3
Dependent Claim
45 words
The method of Claim 1 further comprising: changing the designation of a predetermined one of the virtual pin nodes from one to the other of the input and output functions to thereby provide the predetermined one virtual pin node with a bidirectional signal flow function.
Claim 4
Dependent Claim
106 words
An ASIC emulator for emulating interactions between a yet-to-be developed ASIC and a target system into which the ASIC is to be inserted, the emulator comprising: software modeling means for modeling the ASIC during development: input register means for receiving, storing and outputting ASIC input signals generated by the target system; output register means for receiving, storing and outputting ASIC output signals generated by the software modeling means; and data exchange synchronizing means for transmitting to the software modeling means the ASIC input signals stored in the input register means and for transmitting to the target system, ASIC output signals generated by the software modeling means.
Claim 5
Dependent Claim
106 words
An ASIC emulator for emulating interactions between a yet-to-be developed ASIC and a target system into which the ASIC is to be inserted, the emulator comprising: software modeling means for modeling the ASIC during development: input register means for receiving, storing and outputting ASIC input signals generated by the target system; output register means for receiving, storing and outputting ASIC output signals generated by the software modeling means; and data exchange synchronizing means for transmitting to the software modeling means the ASIC input signals stored in the input register means and for transmitting to the target system, ASIC output signals generated by the software modeling means.
Claim 6
Dependent Claim
65 words
The ASIC emulator of Claim 3 further comprising: a combination of real pins defining a pin dummy, the pin dummy being inserted into the target system at a location where the yet-to-be developed ASIC is to be inserted and being disposed between the software modeling means and the target system so as to channel information exchanged between the software modeling means and the target system.
Claim 7
Independent Claim
126 words
A method for designing and developing an integrated circuit comprising the steps of: defining in software a behavior-level model of the integrated circuit under development; defining in software virtual pin nodes representing real pins of the integrated circuit under development; providing a pin dummy having real pins corresponding to the real pins of the integrated circuit under development; providing real pin register means for storing digital information representing the states of the real pins of the pin dummy; and exchanging information between the real pin register means and the memory cells supporting the virtual pin nodes such that a mirror relationship is established between the software simulated logic states of the virtual pin nodes and the logic states of the real pins on the pin dummy.
Claim 8
Independent Claim
126 words
A method for designing and developing an integrated circuit comprising the steps of: defining in software a behavior-level model of the integrated circuit under development; defining in software virtual pin nodes representing real pins of the integrated circuit under development; providing a pin dummy having real pins corresponding to the real pins of the integrated circuit under development; providing real pin register means for storing digital information representing the states of the real pins of the pin dummy; and exchanging information between the real pin register means and the memory cells supporting the virtual pin nodes such that a mirror relationship is established between the software simulated logic states of the virtual pin nodes and the logic states of the real pins on the pin dummy.
Claim 9
Independent Claim
102 words
A method for developing different portions of a single integrated circuit at different development sites comprising the steps of: partitioning the integrated circuit into model portions; modeling the model portions of the integrated circuit, either in hardware or software, at different locations; providing a real-pin register means for collecting pin information from individual ones of the modelled portions; and exchanging information between virtual pin nodes of the model portions and the real-pin register means so as to establish a mirror relationship between the logic states of the real-pin register means and the virtual-pin nodes of the modelled portions of the integrated circuit.
Claim 10
Independent Claim
102 words
A method for developing different portions of a single integrated circuit at different development sites comprising the steps of: partitioning the integrated circuit into model portions; modeling the model portions of the integrated circuit, either in hardware or software, at different locations; providing a real-pin register means for collecting pin information from individual ones of the modelled portions; and exchanging information between virtual pin nodes of the model portions and the real-pin register means so as to establish a mirror relationship between the logic states of the real-pin register means and the virtual-pin nodes of the modelled portions of the integrated circuit.
References Cited (Backward Citations)
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