Patent US5940698A successfully refreshed from Google Patents.
US5940698A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a semiconductor device having high performance gate electrode structure
Assignee: GlobalFoundries Inc
•
Filing: 1997-12-01
•
Granted: 1999-08-17
•
Expires: 2017-12-01
Abstract
Abstract A semiconductor device having a high performance gate electrode structure and a process of fabricating such a device. A semiconductor device in accordance with an embodiment of the invention is formed by forming a gate insulating layer is over a substrate. A diffusion barrier layer is formed over the gate insulating layer and a trench is formed in the diffusion barrier layer. In the trench, a metal gate electrode is formed. The diffusion barrier layer impedes diffusion of the metal gate electrode into the gate insulating layer during, for example, subsequent processing. The gate insulating layer, the barrier layer, and the gate electrode may, for example, be formed from cobalt niobate, tantalum silicon nitride, and copper, respectively. The copper gate electrode and cobalt gate insulating layer can, for example, increase the speed of the semiconductor device as compared to conventional transistors.
Inventors
- 👤 Mark I Gardner
- 👤 Mark C. Gilmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:32
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/60; H10D62/00; H10D62/80; H10D62/83; H10D64/01304; H10D64/01316; H10D64/01318; H10D64/025; H10D64/027; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62; H10D64/66; H10D64/667; H10D64/68; H10D64/691
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
60 words
A process of fabricating a semiconductor device, comprising: forming a gate insulating layer over a substrate; forming a diffusion barrier layer over the gate insulating layer; forming a trench in the diffusion barrier layer; and forming a metal gate electrode in the trench, wherein the diffusion barrier layer impedes diffusion of the metal gate electrode into the gate insulating layer.
Claim 2
Dependent Claim
60 words
A process of fabricating a semiconductor device, comprising: forming a gate insulating layer over a substrate; forming a diffusion barrier layer over the gate insulating layer; forming a trench in the diffusion barrier layer; and forming a metal gate electrode in the trench, wherein the diffusion barrier layer impedes diffusion of the metal gate electrode into the gate insulating layer.
Claim 3
Dependent Claim
17 words
The process of claim 1, wherein the gate insulating layer has a permittivity greater than silicon dioxide.
Claim 4
Dependent Claim
15 words
The process of claim 1, wherein the gate insulating layer is formed from cobalt niobate.
Claim 5
Dependent Claim
15 words
The process of claim 1, wherein the barrier layer is formed from a conductive material.
Claim 6
Dependent Claim
15 words
The process of claim 1, wherein the barrier layer is formed from tantalum silicon nitride.
Claim 7
Dependent Claim
14 words
The process of claim 1, wherein the metal gate electrode is formed from copper.
Claim 8
Dependent Claim
39 words
The process of claim 1, wherein forming the metal gate electrode in the trench includes: depositing a layer of metal over the substrate to fill the trench; and planarizing the metal layer with a top surface of the trench.
Claim 9
Dependent Claim
26 words
The process of claim 7, further including removing portions of the diffusion barrier layer and gate insulating layer adjacent the gate electrode to expose the substrate.
Claim 10
Dependent Claim
32 words
The process of claim 8, wherein removing portions of the diffusion barrier layer and gate insulating layer includes leaving a region of the diffusion barrier layer on sidewalls of the gate electrode.
Claim 11
Dependent Claim
33 words
The process of claim 1, further including forming elevated active regions on the substrate prior to forming the gate insulating layer, wherein the gate insulating layer is formed between the elevated active regions.
Claim 12
Dependent Claim
27 words
The process of claim 10, wherein forming the trench in the barrier layer includes forming a contact trench in the barrier layer over each elevated active region.
Claim 13
Dependent Claim
32 words
The process of claim 11, further including forming a metal layer over the substrate to fill the trench and the contacts trenches, the metal layer in the contact trenches forming metal contacts.
Claim 14
Dependent Claim
41 words
The process of claim 11, further including forming two dielectric regions in the barrier layer, the dielectric regions isolating a first portion of the barrier layer between the active regions from second portions of the barrier layer over the active regions.
Claim 15
Dependent Claim
89 words
A process of fabricating a semiconductor device comprising: forming elevated active regions over a substrate; forming a gate insulating layer between the active regions; forming a barrier layer over the gate insulating layer and the active regions; forming two dielectric regions isolating a first portion of the barrier layer over the gate insulating layer from second portions of the barrier layer over the active regions; and forming a gate electrode in the first portion and an active region contact in each of the second portions of the barrier layer.
Claim 16
Dependent Claim
89 words
A process of fabricating a semiconductor device comprising: forming elevated active regions over a substrate; forming a gate insulating layer between the active regions; forming a barrier layer over the gate insulating layer and the active regions; forming two dielectric regions isolating a first portion of the barrier layer over the gate insulating layer from second portions of the barrier layer over the active regions; and forming a gate electrode in the first portion and an active region contact in each of the second portions of the barrier layer.
Claim 17
Dependent Claim
17 words
The process of claim 14, wherein the gate insulating layer has a permittivity greater than silicon dioxide.
Claim 18
Dependent Claim
15 words
The process of claim 14, wherein the gate insulating layer is formed from cobalt niobate.
Claim 19
Dependent Claim
15 words
The process of claim 14, wherein the barrier layer is formed from tantalum silicon nitride.
Claim 20
Dependent Claim
48 words
The process of claim 14, wherein forming the two dielectric regions includes: selectively removing portions of the barrier layer to form dielectric trenches separating the first portion of the barrier layer from the second portions of the barrier layer; and filling the dielectric trenches with a dielectric material.
Claim 21
Dependent Claim
16 words
The process of claim 14, wherein the dielectric regions extend down to the gate insulating layer.
Claim 22
Dependent Claim
44 words
The process of claim 14, wherein forming the gate electrode and the active region contacts includes: forming a trench in the first portion of the barrier layer and in each second portion of the barrier layer; and filling the trenches with a conductive material.
Claim 23
Dependent Claim
14 words
The process of claim 20, wherein forming the trenches forms U-shaped barrier layer portions.
References Cited (Backward Citations)
US4784718A
Cited
US5314832A
Cited
US5397909A
Cited
US5716861A
Cited
US5429987A
Cited
US5672530A
Cited
US5501995A
Cited
US5447874A
Cited
US5830810A
Cited
US5688700A
Cited
US5804846A
Cited
US5714398A
Cited
US5677217A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-16 | 2003-02-15 | 2003-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-16 | 2007-02-15 | 2007-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-16 | 2011-02-15 | 2011-08-17 | $7700.00 | Window Closed / Lapsed |