Method of making MOS transistor with controlled shallow source/drain junction

Claim 1

A method of forming a MOS transistor on a substrate of single crystal silicon in an active region of the substrate which is separated by field insulation regions from adjacent active regions, the method comprising the following steps: depositing a layer of insulating material on the substrate, including on the field insulation regions, the deposited layer providing gate insulation on the active region and adding insulating material to the field insulation regions; depositing polycrystalline silicon on said gate insulation to provide a gate electrode and provide insulating side walls on the sides of said gate electrode; etching the insulating material to form source and drain gaps between the field insulation regions and the side walls on opposite sides of the gate, the surface of the substrate being exposed in each said source and drain gap and each said gap having a depth, perpendicular to the surface of the substrate between the field insulation region and the adjacent side wall, of at least 1500 Å; depositing polycrystalline silicon on said substrate to form source and drain electrodes, said source electrode including a source strap portion in said source gap contacting the substrate at a source junction region and including a source interconnect portion extending over the field insulation region adjacent said source gap, and said drain electrode including a drain strap portion in said drain gap contacting the substrate at a drain junction region and including a drain interconnect portion extending over the field insulation region adjacent said drain gap, the deposited polycrystalline silicon being thickest in the source and drain strap portions overlying the respective source and drain junction regions, measured perpendicularly to the substrate, and thinner in the source and drain interconnect portions; implanting doping impurities in the polycrystalline silicon of said source and drain electrodes; rapid thermal annealing at a temperature in the range of between 1050° C. to 1150° C. for less than 40 seconds to diffuse said implanted doping impurities in said electrodes, including diffusing doping impurities through said source and drain electrodes and into the respective source and drain junction regions of said substrate, the effective depth of such diffusion into the substrate being the junction depth of each said source and drain junction region and said junction depth being small in comparison with the thickness of the source and drain strap portions based on the substantially lower rate of impurity diffusion through single crystal silicon versus polycrystalline silicon; and connecting the source and drain electrodes to external MOS transistor interconnects in the source and drain interconnect portions of the respective source and drain electrodes overlying the field insulation regions.

Claim 2

A method of forming a MOS transistor on a substrate of single crystal silicon in an active region of the substrate which is separated by field insulation regions from adjacent active regions, the method comprising the following steps: depositing a layer of insulating material on the substrate, including on the field insulation regions, the deposited layer providing gate insulation on the active region and adding insulating material to the field insulation regions; depositing polycrystalline silicon on said gate insulation to provide a gate electrode and provide insulating side walls on the sides of said gate electrode; etching the insulating material to form source and drain gaps between the field insulation regions and the side walls on opposite sides of the gate, the surface of the substrate being exposed in each said source and drain gap and each said gap having a depth, perpendicular to the surface of the substrate between the field insulation region and the adjacent side wall, of at least 1500 Å; depositing polycrystalline silicon on said substrate to form source and drain electrodes, said source electrode including a source strap portion in said source gap contacting the substrate at a source junction region and including a source interconnect portion extending over the field insulation region adjacent said source gap, and said drain electrode including a drain strap portion in said drain gap contacting the substrate at a drain junction region and including a drain interconnect portion extending over the field insulation region adjacent said drain gap, the deposited polycrystalline silicon being thickest in the source and drain strap portions overlying the respective source and drain junction regions, measured perpendicularly to the substrate, and thinner in the source and drain interconnect portions; implanting doping impurities in the polycrystalline silicon of said source and drain electrodes; rapid thermal annealing at a temperature in the range of between 1050° C. to 1150° C. for less than 40 seconds to diffuse said implanted doping impurities in said electrodes, including diffusing doping impurities through said source and drain electrodes and into the respective source and drain junction regions of said substrate, the effective depth of such diffusion into the substrate being the junction depth of each said source and drain junction region and said junction depth being small in comparison with the thickness of the source and drain strap portions based on the substantially lower rate of impurity diffusion through single crystal silicon versus polycrystalline silicon; and connecting the source and drain electrodes to external MOS transistor interconnects in the source and drain interconnect portions of the respective source and drain electrodes overlying the field insulation regions.