Self-aligned tungsten strapped source/drain and gate technology for deep submicron CMOS

Claim 1

A process for producing a self-aligned tungsten strapped source/drain and gate for a deep submicron CMOS which comprises clearing a wafer, growing a n/p well; making an insulated area using LOCOS; growing a gate oxide, depositing onto the gate oxide poly-Si, processing the wafer through LPCVD to deposit a Si:Ge:B layer using SiH 4 :GeH 4 :B 2 H 6 ; after high temperature annealing, the B in Si:Ge:B layer diffuses into the poly-Si gate to form the p-type poly-Si; subjecting the wafer to poly-Si etching and stacking to SiO 2 or Si 3 N 4 layer to form a spacer after etching; selectively etching the Si:Ge:B layer by a wet etching process; subjecting the wafer to implantation and annealing on the source and drain; then subjecting the wafer to a LPCVD process and filling in with SiH 4 :WF 6 gas to make selective W-CVD; which is followed by depositing BPSG, etching of contact gap, depositing a metal layer and etching in order to finish the device.