Patent US5933434A successfully refreshed from Google Patents.
US5933434A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory system having internal state monitoring circuit
Assignee: Round Rock Research LLC
•
Filing: 1997-01-28
•
Granted: 1999-08-03
•
Expires: 2017-01-28
Abstract
Abstract A memory system having a test mode which can be used to access signals internally generated by the system during its operation. The signals accessible in the test mode are not available to a standard user of the system, but can be used by a memory chip designer to determine the cause of a device failure. The memory system includes a test signal switch which is used to route one of a multitude of internal signals to an input/output (I/O) pad where the information can be accessed by a chip designer. In order to access the internal signals, the memory system is first placed into a test mode, which acts to shut off the data paths used for reading the output of the sense amplifier included as part of the data read path or for reading the contents of the status register. A signal specifying a particular test signal of interest is then input. Decode logic is used to verify the coded input signal and control the multiplexer to route a specified internal signal through the switch to the I/O pad. By operating the memory system and monitoring the selected signal or data, a chip designer can isolate the cause of a device failure and investigate solutions to the problem without the need for micro-probing of the device.
Inventors
- 👤 Frankie F. Roohparvar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:10
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48; G11C29/12; G11C29/14; G11C7/00; G11C7/10; G11C29/46
Claims Analysis
Total Claims: 71
Claim 1
Independent Claim
171 words
A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which internal signals used to monitor the memory system can be accessed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the memory system comprising: a test mode detector which detects the test, mode access state for accessing the test mode of operation, wherein the test mode access state is different from states which occur during the standard mode of operation; a switch which selects one of a plurality of internal signals input to the switch and routes that internal signal, in real time, to a data output node when the test mode of operation is accessed, wherein the internal signals monitor the operation of the memory system; and the data output node to which the selected internal signal is routed by the switch.
Claim 2
Dependent Claim
171 words
A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which internal signals used to monitor the memory system can be accessed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the memory system comprising: a test mode detector which detects the test, mode access state for accessing the test mode of operation, wherein the test mode access state is different from states which occur during the standard mode of operation; a switch which selects one of a plurality of internal signals input to the switch and routes that internal signal, in real time, to a data output node when the test mode of operation is accessed, wherein the internal signals monitor the operation of the memory system; and the data output node to which the selected internal signal is routed by the switch.
Claim 3
Dependent Claim
23 words
The memory system of claim 1, wherein the internal signals for monitoring the operation of the memory system include digital and analog signals.
Claim 4
Dependent Claim
39 words
The memory system of claim 1, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.
Claim 5
Dependent Claim
23 words
The memory system of claim 3, wherein a plurality of test mode access signals are used to access the test mode of operation.
Claim 6
Dependent Claim
48 words
The memory system of claim 3, wherein the test mode detector detects whether the test mode access signal has a voltage outside a range of voltages applied during operation in the standard mode of the memory system in order to permit access to the test mode of operation.
Claim 7
Dependent Claim
20 words
The memory system of claim 1, wherein the data output node is a data input/output pad of the memory system.
Claim 8
Dependent Claim
19 words
The memory system of claim 1, wherein the data output node is an address pin of the memory system.
Claim 9
Dependent Claim
33 words
The memory system of claim 1, wherein the switch further comprises: a digital test signal switch which selects which of a plurality of digital signals is accessed in the test mode of operation.
Claim 10
Dependent Claim
33 words
The memory system of claim 1, wherein the switch further comprises: an analog test signal switch which selects which of a plurality of analog signals is accessed in the test mode of operation.
Claim 11
Dependent Claim
63 words
The memory system of claim 1, further comprising: a controller which controls the switch to select which of the plurality of internal signals is routed by the switch in the test mode of operation, wherein the controller responds to a signal indicative of which of the plurality of internal signals is to be routed by routing that signal to the data output node.
Claim 12
Dependent Claim
38 words
The memory system of claim 1, wherein the test mode access state which permits access to the test mode is detection of a sequence of command signals which would not be applied during the standard mode of operation.
Claim 13
Independent Claim
188 words
A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising: applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation; verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation; selecting which of a plurality of internal signals for monitoring the memory system is routed to a data output node when the test mode of operation is accessed; and routing the selected signal to the data output node in real time when the test mode of operation is accessed.
Claim 14
Independent Claim
188 words
A method of accessing internal signals generated by a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which internal signals used to monitor the memory system can be accessed, where access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the method comprising: applying a test mode access signal to produce the test mode access state for entering the test mode of operation, wherein the test mode access state is different from states produced during the standard mode of operation; verifying that the test mode access state produced is a valid one allowing entry to the test mode of operation; selecting which of a plurality of internal signals for monitoring the memory system is routed to a data output node when the test mode of operation is accessed; and routing the selected signal to the data output node in real time when the test mode of operation is accessed.
Claim 15
Dependent Claim
29 words
The method of accessing internal signals generated by a memory system of claim 12, wherein the internal signals used to monitor the memory system include digital and analog signals.
Claim 16
Dependent Claim
47 words
The method of accessing internal signals generated by a memory system of claim 12, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is different than signals applied during the standard mode of operation.
Claim 17
Dependent Claim
64 words
The method of accessing internal signals generated by a memory system of claim 14, wherein the step of verifying that the test mode access state produced is a valid one further comprises: determining if the test mode access signal applied to enter the test mode is a voltage outside a range of voltages applied during operation in the standard mode of the memory system.
Claim 18
Dependent Claim
31 words
The method of accessing internal signals generated by a memory system of claim 12, wherein a plurality of test mode access signals are used to produce the test mode access state.
Claim 19
Dependent Claim
29 words
The method of accessing internal signals generated by a memory system of claim 12, wherein the selected signal is routed to a data input/output pad of the memory system.
Claim 20
Dependent Claim
28 words
The method of accessing internal signals generated by a memory system of claim 12, wherein the selected signal is routed to an address pin of the memory system.
Claim 21
Dependent Claim
46 words
The method of accessing internal signals generated by a memory system of claim 12, wherein the test mode access signal which produces the test mode access state is a sequence of command signals different from those which would be applied during the standard mode of operation.
Claim 22
Dependent Claim
157 words
A data processing system having a standard mode of operation in which a user can perform data processing functions and a test mode of operation in which internal signals used to monitor the data processing system can be accessed, where access to the test mode of operation is based on detection of a test mode access state which is different from states which occur during the standard mode of operation, the data processing system comprising: a test mode access state detector which detects a test mode access signal used to produce the test mode access state; a switch which selects one of a plurality of internal signals input to the switch and routes the selected internal signal, in real time, to a data output node when the test mode of operation is accessed, wherein the internal signals monitor the data processing system; and the data output node to which the selected signal is routed by the switch.
Claim 23
Dependent Claim
157 words
A data processing system having a standard mode of operation in which a user can perform data processing functions and a test mode of operation in which internal signals used to monitor the data processing system can be accessed, where access to the test mode of operation is based on detection of a test mode access state which is different from states which occur during the standard mode of operation, the data processing system comprising: a test mode access state detector which detects a test mode access signal used to produce the test mode access state; a switch which selects one of a plurality of internal signals input to the switch and routes the selected internal signal, in real time, to a data output node when the test mode of operation is accessed, wherein the internal signals monitor the data processing system; and the data output node to which the selected signal is routed by the switch.
Claim 24
Dependent Claim
25 words
The data processing system of claim 20, wherein the data processing system includes a memory system which generates the internal signals routed by the switch.
Claim 25
Dependent Claim
22 words
The data processing system of claim 20, wherein the internal signals for monitoring the data processing system include digital and analog signals.
Claim 26
Dependent Claim
24 words
The data processing system of claim 20, wherein a plurality of test mode access signals are used to produce the test mode access state.
Claim 27
Dependent Claim
35 words
The data processing system of claim 20, wherein the switch further comprises: a digital test signal switch which selects which one of a plurality of digital signals is accessed in the test mode of operation.
Claim 28
Dependent Claim
35 words
The data processing system of claim 20, wherein the switch further comprises: an analog test signal switch which selects which one of a plurality of analog signals is accessed in the test mode of operation.
Claim 29
Dependent Claim
41 words
The data processing system of claim 20, wherein the test mode access state detector detects whether the test mode access signal has a voltage outside a range of voltages applied during operation in the standard mode of the data processing system.
Claim 30
Dependent Claim
40 words
The data processing system of claim 20, wherein the test mode access state detector detects a sequence of command signals which would not be applied during the standard mode of operation in order to produce the test mode access state.
Claim 31
Dependent Claim
216 words
A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which internal signals indicative of the operation of the memory system and generated by the system during the standard mode of operation can be accessed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the memory system comprising: a controller which generates a plurality of internal signals indicative of the operation of the memory system, wherein the internal signals are generated by the controller during the standard mode of operation; a test mode detector which detects the test mode access state for accessing the test mode of operation, wherein the test mode access state is different from states which occur during the standard mode of operation; a signal selector switch which selects which one of the plurality of internal signals indicative of the operation of the memory system input to the signal selector switch is routed to a data output node in real time when the test mode of operation is accessed; and the data output node to which the selected signal is routed by the signal selector switch.
Claim 32
Dependent Claim
216 words
A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which internal signals indicative of the operation of the memory system and generated by the system during the standard mode of operation can be accessed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from states which occur during the standard mode of operation, the memory system comprising: a controller which generates a plurality of internal signals indicative of the operation of the memory system, wherein the internal signals are generated by the controller during the standard mode of operation; a test mode detector which detects the test mode access state for accessing the test mode of operation, wherein the test mode access state is different from states which occur during the standard mode of operation; a signal selector switch which selects which one of the plurality of internal signals indicative of the operation of the memory system input to the signal selector switch is routed to a data output node in real time when the test mode of operation is accessed; and the data output node to which the selected signal is routed by the signal selector switch.
Claim 33
Dependent Claim
23 words
The memory system of claim 28, wherein the internal signals indicative of the operation of the memory system include digital and analog signals.
Claim 34
Dependent Claim
42 words
The memory system of claim 28, wherein the test mode access state which permits access to the test mode is detection of a test mode access signal which is outside of a range of signals applied during the standard mode of operation.
Claim 35
Dependent Claim
23 words
The memory system of claim 30, wherein a plurality of test mode access signals are used to access the test mode of operation.
Claim 36
Dependent Claim
27 words
The memory system of claim 28, wherein the data output node to which the selected signal is routed is a data input/output pad of the memory system.
Claim 37
Dependent Claim
26 words
The memory system of claim 28, wherein the data output node to which the selected signal is routed is an address pin of the memory system.
Claim 38
Dependent Claim
36 words
The memory system of claim 28, wherein the signal selector switch further comprises: a digital test signal switch which selects which one of a plurality of digital signals is accessed in the test mode of operation.
Claim 39
Dependent Claim
36 words
The memory system of claim 28, wherein the signal selector switch further comprises: an analog test signal switch which selects which one of a plurality of analog signals is accessed in the test mode of operation.
Claim 40
Dependent Claim
48 words
The memory system of claim 30, wherein the test mode detector detects whether the test mode access signal has a voltage outside a range of voltages applied during operation in the standard mode of the memory system in order to permit access to the test mode of operation.
Claim 41
Dependent Claim
65 words
The memory system of claim 28, further comprising: a second controller which controls the signal selector switch to select which of the plurality of signals is routed by the switch in the test mode of operation, wherein the second controller responds to a signal indicative of which of the plurality of signals is to be routed by routing that signal to the data output node.
Claim 42
Dependent Claim
38 words
The memory system of claim 28, wherein the test mode access state which permits access to the test mode is detection of a sequence of command signals which would not be applied during the standard mode of operation.
Claim 43
Dependent Claim
65 words
An integrated circuit memory device comprising: test mode detection circuitry for detecting an externally provided test mode trigger and initiating a test mode in response to the test mode trigger; and output circuitry coupled to the test mode detection circuitry, said output circuitry configured to selectively output internal operating signals, in real time, acquired during standard memory operations in response to the initiated test mode.
Claim 44
Dependent Claim
65 words
An integrated circuit memory device comprising: test mode detection circuitry for detecting an externally provided test mode trigger and initiating a test mode in response to the test mode trigger; and output circuitry coupled to the test mode detection circuitry, said output circuitry configured to selectively output internal operating signals, in real time, acquired during standard memory operations in response to the initiated test mode.
Claim 45
Dependent Claim
44 words
The integrated circuit memory device of claim 39, wherein the test mode detection circuitry is configured to monitor an external connection voltage for a high voltage which exceeds a predetermined level and to initiate a test mode in response to a detected high voltage.
Claim 46
Dependent Claim
46 words
The integrated circuit memory device of claim 39, wherein the test mode detection circuitry monitors two external connection voltages for high voltages which each exceed a predetermined level and initiates a test mode in response to two simultaneously detected high voltage on the two external connections.
Claim 47
Dependent Claim
30 words
The integrated circuit memory device of claim 39, wherein the output circuitry comprises a switching circuit for coupling one of a plurality of internal operating signals to an external connection.
Claim 48
Dependent Claim
16 words
The integrated circuit memory device of claim 42, wherein the switching circuit comprises a multiplex circuit.
Claim 49
Dependent Claim
20 words
The integrated circuit memory device of claim 39, wherein the internal operating signals are either analog or digital test signals.
Claim 50
Dependent Claim
29 words
The integrated circuit memory device of claim 39, wherein the standard memory operations are performed during the test mode and comprise data read, data write, and data erase operations.
Claim 51
Dependent Claim
58 words
The integrated circuit memory device of claim 39, wherein the internal operating signals are selected from a pre-program signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, or a maximum pulse allowed signal, all acquired during a standard memory erase operation.
Claim 52
Dependent Claim
98 words
A flash memory comprising: an array of non-volatile memory cells; command control circuitry for controlling data program, data read and data erase operations on the array of non-volatile memory cells; a test mode detection circuit configured to detect an externally provided test mode trigger and to initiate a test mode in response to the externally provided test mode trigger; and output circuitry coupled to the test mode detection circuit and configured to selectively output internal operating signals, in real time, acquired during data program, data read and data erase operations while the memory is in the test mode.
Claim 53
Dependent Claim
98 words
A flash memory comprising: an array of non-volatile memory cells; command control circuitry for controlling data program, data read and data erase operations on the array of non-volatile memory cells; a test mode detection circuit configured to detect an externally provided test mode trigger and to initiate a test mode in response to the externally provided test mode trigger; and output circuitry coupled to the test mode detection circuit and configured to selectively output internal operating signals, in real time, acquired during data program, data read and data erase operations while the memory is in the test mode.
Claim 54
Dependent Claim
42 words
The flash memory of claim 47, wherein the test mode detection circuitry comprises: a first high voltage detector circuit coupled to an external address pad configured to detect when a voltage provided on the external address pad exceeds a predetermined voltage level.
Claim 55
Dependent Claim
44 words
The flash memory of claim 48, wherein the test mode detection circuitry further comprises: a second high voltage detector circuit coupled to a second external connection and configured to detect when a voltage provided on the second external connection exceeds a predetermined voltage level.
Claim 56
Dependent Claim
35 words
The flash memory of claim 49, wherein the test mode detection circuitry further comprises: a test mode code latch circuit for latching a test mode code signal provided on a plurality of data input connections.
Claim 57
Independent Claim
68 words
A method of testing an integrated memory device, comprising the steps of: initiating a test mode of operation of the integrated memory device; selecting one of a data program, data read and data erase operation of the integrated memory device; performing the selected operation during the test mode; and selectively outputting internal signals from the integrated memory device generated during performance of the selected operation in real time.
Claim 58
Independent Claim
68 words
A method of testing an integrated memory device, comprising the steps of: initiating a test mode of operation of the integrated memory device; selecting one of a data program, data read and data erase operation of the integrated memory device; performing the selected operation during the test mode; and selectively outputting internal signals from the integrated memory device generated during performance of the selected operation in real time.
Claim 59
Dependent Claim
16 words
The method of claim 51, wherein the test mode is initiated using an externally provided signal.
Claim 60
Dependent Claim
24 words
The method of claim 52, wherein the externally provided signal is a voltage provided on an external connection which exceeds a predetermined voltage level.
Claim 61
Dependent Claim
62 words
The method of claim 51, wherein the step of selectively outputting comprises the steps of: selecting one of the internal signals to be output on an external connection; and coupling the one of the internal signals to the external connection so that the one of the internal signals can be monitored in real time during the step of performing the selected operation.
Claim 62
Dependent Claim
15 words
The method of claim 51, wherein the internal signals are either digital or analog signals.
Claim 63
Dependent Claim
25 words
The method of claim 51, wherein the test mode is initiated using a plurality of externally provided signals provided on a plurality of external connections.
Claim 64
Dependent Claim
34 words
The method of claim 51, wherein the step of initiating a test mode of operation comprises the step of: detecting a voltage provided on an external address connection which exceeds a predetermined voltage level.
Claim 65
Dependent Claim
35 words
The method of claim 57, wherein the step of initiating a test mode of operation further comprises the step of: detecting a voltage provided on a second external connection which exceeds a predetermined voltage level.
Claim 66
Dependent Claim
34 words
The method of claim 58, wherein the step of initiating a test mode of operation further comprises the step of: latching a test mode code signal provided on a plurality of data input connections.
Claim 67
Dependent Claim
64 words
The method of claim 51, wherein the step of initiating a test mode of operation comprises the steps of: detecting a voltage provided on a first external connection which exceeds a predetermined voltage level; detecting a voltage provided on a second external connection which exceeds a predetermined voltage level; and latching a test mode code signal provided on a plurality of data input connections.
Claim 68
Independent Claim
93 words
A method of real time monitoring internal operating signals in a memory device, the method comprising the steps of: externally providing a test mode initiation signal to the memory device; initiating a test mode of operation of the memory device in response to a received test mode initiation signal; performing a standard memory operation on the memory device; and selectively coupling an internal signal, during the step of performing a standard memory operation, to an external connection of the memory device in real time while the memory device is in the test mode.
Claim 69
Independent Claim
93 words
A method of real time monitoring internal operating signals in a memory device, the method comprising the steps of: externally providing a test mode initiation signal to the memory device; initiating a test mode of operation of the memory device in response to a received test mode initiation signal; performing a standard memory operation on the memory device; and selectively coupling an internal signal, during the step of performing a standard memory operation, to an external connection of the memory device in real time while the memory device is in the test mode.
Claim 70
Dependent Claim
16 words
The method of claim 61, wherein the standard memory operation is a memory cell erase operation.
Claim 71
Dependent Claim
59 words
The method of claim 61, wherein the step of selectively coupling the internal signal further comprises the step of: selecting at least one operation of a pre-program signal, an erase high voltage signal, a verify signal, a verify ok signal, an increment address signal, an increment pulse signal, a maximum address detection signal, and a maximum pulse allowed signal.
References Cited (Backward Citations)
US4504784A
Cited
US4550289A
Cited
US4839865A
Cited
US5157629A
Cited
US4970454A
Cited
US5233610A
Cited
US5196787A
Cited
US5107208A
Cited
US5030904A
Cited
US5498972A
Cited
US5177745A
Cited
US5253255A
Cited
US5642057A
Cited
US5459733A
Cited
US5212442A
Cited
US5463585A
Cited
US5581176A
Cited
US5627838A
Cited
US5657328A
Cited
US5508631A
Cited
US5648730A
Cited
US5627478A
Cited
US5619461A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |