Semiconductor device incorporating voltage reduction circuit therein

Claim 2

A semiconductor device comprising storage means having a data input/output node and a power node provided independently of said data input/output node, said storage means inputting and operating on a voltage supplied to said power node, storing data transferred thereto through said data input/output node and outputting data stored therein to said data input/output node, a power terminal supplied with a power supply voltage, means coupled to said power terminal for generating a power-down voltage smaller than said power supply voltage, and means for supplying said power node of said storage means with said power-down voltage in a test mode and with said power supply voltage in a normal operation mode.

Claim 3

The semiconductor device as claimed in claim 1; and further comprising a data line, a switch means connected between said data input/output node and said data line, and a selection signal generating means for generating a selection signal, said selection signal generating means being connected to said switch means, said switch means connecting said data input/output node and said data line in response to said selection signal from said selection signal generating means.

Claim 4

A semiconductor device comprising plurality of word lines; a plurality of bit lines; a power line; a plurality of memory cells each disposed at a different one of intersections of said word lines and said bit lines and being connected to said power line; a data read/write control circuit for selecting one of said word lines and one of said bit lines to designate at least one of said the memory cells in response to address signals and performing a data read/write operation on said at least one of said memory; a power terminal receiving a power supply voltage; and a voltage supply control circuit connected to said power terminal and said power line to supply said power supply line with said power supply voltage during a normal operation mode and with a power-down voltage smaller than said power supply voltage during a test mode.

Claim 5

A semiconductor device comprising plurality of word lines; a plurality of bit lines; a power line; a plurality of memory cells each disposed at a different one of intersections of said word lines and said bit lines and being connected to said power line; a data read/write control circuit for selecting one of said word lines and one of said bit lines to designate at least one of said the memory cells in response to address signals and performing a data read/write operation on said at least one of said memory; a power terminal receiving a power supply voltage; and a voltage supply control circuit connected to said power terminal and said power line to supply said power supply line with said power supply voltage during a normal operation mode and with a power-down voltage smaller than said power supply voltage during a test mode.

Claim 6

The semiconductor device as claimed in claim 3, wherein said voltage supply control circuit further supplies said data read/write control circuit with said power supply voltage during both of said normal operation mode and said test mode.

Claim 7

A semiconductor device comprising a storage area, a control circuit for performing a data read/write operation to read and write data from and into said storage area, a power terminal receiving a power supply voltage, means coupled to said power terminal for generating a power-down voltage smaller than said power supply voltage at said power terminal independently of a current flowing through said storage area, and voltage supply means for supplying said power supply voltage to both of said storage area and said control circuit during a normal operation mode and supplying said power supply voltage and said power-down voltage to said control circuit and said storage area, respectively, during a test mode.

Claim 8

A semiconductor device comprising a storage area, a control circuit for performing a data read/write operation to read and write data from and into said storage area, a power terminal receiving a power supply voltage, means coupled to said power terminal for generating a power-down voltage smaller than said power supply voltage at said power terminal independently of a current flowing through said storage area, and voltage supply means for supplying said power supply voltage to both of said storage area and said control circuit during a normal operation mode and supplying said power supply voltage and said power-down voltage to said control circuit and said storage area, respectively, during a test mode.

Claim 9

The semiconductor device as claimed in claim 2, wherein said means coupled to said power terminal include first and second power nodes supplied with first and second voltage, respectively, a third power node coupled to said storage area, and a control node supplied with a control signal, and further include first means for supplying said third power node with said first voltage at said first power node when said control signal takes a first logic level, and second means for supplying said third power node with said second voltage at said second power node when said control signal takes a second logic level different from said first logic level.

Claim 10

The semiconductor device as claimed in claim 6, wherein said control signal is supplied from said control circuit.