US4550289A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1982-12-27
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Granted: 1985-10-29
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Expires: 2002-12-27
Abstract
Abstract A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.
Inventors
- 👤 Katsuhiko Kabashima
- 👤 Yoshihiro Takemae
- 👤 Shigeki Nozaki
- 👤 Tsuyoshi Ohira
- 👤 Hatsuo Miyahara
- 👤 Masakazu Kanai
- 👤 Seiji Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G06; G06F; G06F11/00; G06F11/006
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
260 words
A semiconductor integrated circuit device fabricated in and on a single chip having a normal operation mode and a test mode, and having at least one external input/ouput/detection (I/O/D) pin operatively connected to receive a first or second voltage level, comprising: at least one internal test node selectively having one of a ground level and a power source level in accordance with the mode of the device; and a test circuit formed in the single chip, comprising: a MIS transistor having a gate operatively connected to said at least one internal test node, having a drain operatively connected to ground level and having a source, said MIS transistor selectively having one of a first threshold voltage and a second threshold voltage, the second threshold voltage being higher than said first threshold voltage in accordance with said at least one internal test node, respectively being at the power source level or ground level; and a MIS diode, operatively connected in series between said source of said MIS transistor and the at least one external I/O/D pin, said MIS diode being reverse biased during the normal operation mode, said test circuit determining whether the ground level or the power source level is at said at least one internal test node, in accordance with a detection of the first voltage level or the second voltage level applied to the at least one external I/O/D pin, and capable of drawing a current therefrom, the first voltage level and the second voltage level being outside the range between the power source level and ground level.
Claim 2
Dependent Claim
260 words
A semiconductor integrated circuit device fabricated in and on a single chip having a normal operation mode and a test mode, and having at least one external input/ouput/detection (I/O/D) pin operatively connected to receive a first or second voltage level, comprising: at least one internal test node selectively having one of a ground level and a power source level in accordance with the mode of the device; and a test circuit formed in the single chip, comprising: a MIS transistor having a gate operatively connected to said at least one internal test node, having a drain operatively connected to ground level and having a source, said MIS transistor selectively having one of a first threshold voltage and a second threshold voltage, the second threshold voltage being higher than said first threshold voltage in accordance with said at least one internal test node, respectively being at the power source level or ground level; and a MIS diode, operatively connected in series between said source of said MIS transistor and the at least one external I/O/D pin, said MIS diode being reverse biased during the normal operation mode, said test circuit determining whether the ground level or the power source level is at said at least one internal test node, in accordance with a detection of the first voltage level or the second voltage level applied to the at least one external I/O/D pin, and capable of drawing a current therefrom, the first voltage level and the second voltage level being outside the range between the power source level and ground level.
Claim 3
Dependent Claim
70 words
A semiconductor integrated circuit device as set forth in claim 1, wherein the first voltage level corresponds to a plus and minus threshold level of said MIS transistor and MIS diode when said at least one internal test node is at the power source level and the second voltage level corresponds to two times the minus threshold level when said at least one internal test node is at ground level.
Claim 4
Dependent Claim
59 words
A semiconductor integrated circuit as set forth in claim 2, wherein said MIS transistor substantially forms a conductive path if said at least one internal test node is at the power source level and substantially forms a transistor in which said gate and drain are electrically shorted if said at least one internal test node is at ground level.
Claim 5
Dependent Claim
37 words
A semiconductor integrated circuit as set forth in claim 3, further comprising a pad mounted on the single chip, wherein said MIS diode and the at least one external I/O/D pin are operatively connected to said pad.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-28 | 1989-04-29 | 1989-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-28 | 1993-04-29 | 1993-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-28 | 1997-04-29 | 1997-10-29 | $7700.00 | Window Closed / Lapsed |