Low voltage interface circuit with a high voltage tolerance

Claim 1

An interface circuit that is configurable to form an input circuit or an output circuit of an integrated circuit that operates in response to a positive supply voltage and a ground supply voltage, the interface circuit comprising: an input/output (I/O) pin for providing a connection to an external circuit; a pull-up structure for pulling up a voltage on said I/O pin; a pull-down structure for pulling down a voltage on said I/O pin; an impedance control circuit for providing control signals to the pull-up and pull-down structures, wherein the control signals disable the pull-up and pull-down structures when the interface circuit is configured as an input circuit, and wherein the control signals enable one of the pull-up and pull-down structures and disable the other one of the pull-up and pull-down structures when the interface circuit is configured as an output circuit; a pull-up protection structure for protecting said pull-up structure from a voltage on said I/O pin greater than the positive supply voltage when the interface circuit is configured as an input circuit; a pull-down protection structure for protecting said pull-down structure from a voltage on said I/O pin greater than the positive supply voltage when the interface circuit is configured as an input circuit; a reference voltage circuit for providing an intermediate voltage to said pull-up protection structure when the interface circuit is configured as an input circuit, the intermediate voltage being less than the positive supply voltage and greater than a ground supply voltage, the intermediate voltage enabling the pull-up protection structure to protect the pull-up structure from voltages on the I/O pin that are greater than the positive supply voltage; wherein said pull-up structure comprises: a first PMOS transistor having a source coupled to receive the positive supply voltage, a drain coupled to the pull-up protection structure, and a gate coupled to receive a control signal from the impedance control circuit; a second PMOS transistor having a source coupled to the drain of the first PMOS transistor and a drain coupled to the I/O pin; voltage control circuitry coupled to a gate of the second PMOS transistor; said pull-down structure comprises an NMOS transistor having a source coupled to receive the ground supply voltage, a drain coupled to the pull-down protection structure, and a gate coupled to receive a control signal from the impedance control circuit; and wherein the voltage control circuitry comprises: a third PMOS transistor coupled between the gate of the second PMOS transistor and the I/O pin, the third PMOS transistor having a gate coupled to the reference voltage circuit, wherein the third PMOS transistor receives the intermediate voltage from the reference voltage circuit when the interface circuit is configured as an input circuit; a third NMOS transistor having a drain connected to the gate of the second PMOS transistor, and a gate coupled to receive the positive supply voltage; and a fourth NMOS transistor having a drain connected to a source of the third NMOS transistor, a source coupled to receive the ground supply voltage, and a gate coupled to receive a logic high control signal when the interface circuit is configured as an input circuit.