5 volt driver in a 3 volt CMOS process

Claim 2

A voltage level shifter comprising: a pull-up device coupled between a voltage supply and an node, and being responsive to a first voltage signal; a pull-down device coupled between the node and a reference voltage supply, and being responsive to a second voltage signal; and a feedback circuit coupled to the pull-down device and the node, wherein a level shifted voltage is provided at the node.

Claim 3

The shifter of claim 1 further comprising: a first bias device coupled between another voltage supply and the node, and responsive to the other voltage supply; and a second bias device coupled between the other voltage supply and a pull-down device node, and being responsive to the second voltage signal.

Claim 4

The shifter of claim 1 wherein a pad driver is coupled to the node.

Claim 5

The shifter of claim 1 wherein the pull-down device utilizes a body effect to prevent a detrimental voltage drop.

Claim 6

The shifter of claim 1 wherein the pull-up device includes two PMOS transistors.

Claim 7

The shifter of claim 1 wherein the pull-down device includes first and second PMOS transistors coupled in series with first and second NMOS transistors, respectively.

Claim 8

The shifter of claim 6 wherein the PMOS transistors utilize a body effect to prevent a detrimental voltage drop.

Claim 9

The shifter of claim 2 wherein the first bias circuit includes at least one NMOS transistor.

Claim 10

The shifter of claim 2 wherein the second bias circuit includes at least one NMOS transistor coupled to the pull-down device node.

Claim 11

The shifter of claim 9 wherein each NMOS transistor utilizes a body effect to prevent a detrimental voltage drop.

Claim 12

The shifter of claim 1 wherein the feedback circuit comprises an NMOS transistor and a PMOS transistor, wherein the feedback circuit is coupled to the pull-up and pull-down devices, coupled to receive the second voltage signal and responsive to a voltage of another voltage supply.

Claim 13

A CMOS voltage level shifter comprising: a first switch coupled between a first voltage supply and a first node; a second switch coupled between the first voltage supply and a second node, the first switch being responsive to a voltage at the second node and the second switch being responsive to a voltage at the first node; a first series of switches coupled between the first node and a reference voltage, one of the first series of switches responsive to a voltage signal; a second series of switches coupled between the second node and the reference voltage, one of the second series of switches being responsive to a complement of the voltage signal; a first pair of switches coupled to the first series of switches and coupled to receive the complement of the voltage signal; and a second pair of switches coupled to the second series of switches and coupled to receive the voltage signal, wherein a level shifted voltage is output from the second node.

Claim 14

A CMOS voltage level shifter comprising: a first switch coupled between a first voltage supply and a first node; a second switch coupled between the first voltage supply and a second node, the first switch being responsive to a voltage at the second node and the second switch being responsive to a voltage at the first node; a first series of switches coupled between the first node and a reference voltage, one of the first series of switches responsive to a voltage signal; a second series of switches coupled between the second node and the reference voltage, one of the second series of switches being responsive to a complement of the voltage signal; a first pair of switches coupled to the first series of switches and coupled to receive the complement of the voltage signal; and a second pair of switches coupled to the second series of switches and coupled to receive the voltage signal, wherein a level shifted voltage is output from the second node.

Claim 15

The shifter of claim 12 wherein the first series of switches includes a first series node and the second series of switches includes a second series node, the level shifter further comprising: a third pair of switches coupled between the first and second series nodes, coupled to a second voltage supply and respectively responsive to the first and second pairs of switches.

Claim 16

The shifter of claim 13 further comprising a fourth pair of switches coupled between a second voltage supply and the first and second nodes, respectively, and controlled by the second voltage supply.

Claim 17

The shifter of claim 12 wherein the second node is coupled to a pad driver to provide the level shifted voltage.

Claim 18

The shifter of claim 15 wherein the pad driver comprises pull-up switches and pull-down switches, at least two of the switches are biased by respective bias voltages and the two switches utilize a body effect to prevent damage to the other switches, so that the pad driver outputs a voltage ranging from the reference voltage to a voltage of the first voltage supply.

Claim 19

A voltage level shifter circuit comprising: a first device to pull up a voltage at a first node; a second device to pull down a voltage at a second node; and a third device coupled to the nodes to prevent the voltage at the first node from dropping below a predetermined voltage and to prevent the voltage at the second node from exceeding a predetermined voltage.

Claim 20

A voltage level shifter circuit comprising: a first device to pull up a voltage at a first node; a second device to pull down a voltage at a second node; and a third device coupled to the nodes to prevent the voltage at the first node from dropping below a predetermined voltage and to prevent the voltage at the second node from exceeding a predetermined voltage.

Claim 21

The circuit of claim 17 further comprising feedback circuitry coupled to the first node and the third device.

Claim 22

The circuit of claim 18 wherein the voltage at the second node is controllable by the feedback circuitry.

Claim 23

The circuit of claim 17 further comprising a fourth device coupled to the first node and the third device.

Claim 24

The circuit of claim 17 wherein the voltage at the first node is greater than the predetermined voltage.

Claim 27

The method of claim 22 further comprising the step of providing a bias current so that the level shifted voltage will not drop below a predetermined voltage.

Claim 28

The method of claim 22 further comprising the step of providing bias current to prevent a damaging voltage drop.