US5319258A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable output drive circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-10-05
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Granted: 1994-06-07
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Expires: 2012-10-05
Abstract
Abstract A programmable output driver circuit is provided having multiple drive capabilities for optimising noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.
Inventors
- 👤 J. Eric Ruetz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:13
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
146 words
A programmable output driver circuit, comprising: a first driver unit, coupled between an input and an output, having a first drive capability; a second driver unit, coupled to said input and said output in parallel to said first driver unit, having a second drive capability different from said first drive capability; and a selector coupled to said second driver unit for selectively enabling and disabling said second driver unit to add or not add said second capability to said first capability, wherein said selector has an associated delay time in adding said second drive capability to said first drive capability, and said driver circuit further comprises a delay circuit coupled between said input and said first driver unit, for delaying an input signal to said first driver circuit by said associated delay time so that application of said first and said second drive capabilities is synchronized.
Claim 2
Dependent Claim
146 words
A programmable output driver circuit, comprising: a first driver unit, coupled between an input and an output, having a first drive capability; a second driver unit, coupled to said input and said output in parallel to said first driver unit, having a second drive capability different from said first drive capability; and a selector coupled to said second driver unit for selectively enabling and disabling said second driver unit to add or not add said second capability to said first capability, wherein said selector has an associated delay time in adding said second drive capability to said first drive capability, and said driver circuit further comprises a delay circuit coupled between said input and said first driver unit, for delaying an input signal to said first driver circuit by said associated delay time so that application of said first and said second drive capabilities is synchronized.
Claim 3
Dependent Claim
29 words
The driver circuit of claim 1 further comprising a memory for storing selectable operating conditions, said memory activating said selector for predetermined input conditions requiring a combined drive capability.
References Cited (Backward Citations)
JPS59158623A
Cited
US4719369A
Cited
EP0253914A1
Cited
US4815113A
Cited
EP0315473A2
Cited
US4820942A
Cited
JPH01284107A
Cited
JPH0258925A
Cited
US4885485A
Cited
US5003205A
Cited
US5097152A
Cited
US5047711A
Cited
JPH03117020A
Cited
US5121013A
Cited
US5089722A
Cited
US5153457A
Cited
US5162672A
Cited
US5153450A
Cited
EP1264470A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |