High speed output buffer circuit with overlap current control

Claim 2

An output buffer circuit having a data input terminal for receiving a data signal, and an output signal terminal for providing an output signal, comprising: an input stage for receiving the data signal from the data input terminal and for providing input stage outputs; a pre-driver stage for receiving the input stage outputs and for providing first and second outputs in response to the input stage outputs, said first output becoming logically low after a first predetermined controlled delay period after said second output becomes logically low, and said second output becoming logically high after a second predetermined controlled delay period after said first output becomes logically high; and an output driver stage for receiving said first and second outputs from the pre-driver stage and for providing the output signal to the output signal terminal, said output driver stage including at least one complementary pair of serially connected output transistor devices, and said output signal being derived at a node between said serially connected output transistor devices, said first and second outputs of the pre-driver stage being supplied only to said output driver stage and not to said input stage.

Claim 3

An output buffer circuit according to claim 1 wherein said input stage comprises a first logic gate and a second logic gate each having at least one input and an output, said inputs of the first and second logic gates being connected together for receiving the data signal.

Claim 4

An output buffer circuit according to claim 1 wherein said pre-driver stage comprises: a first pair of transistors being serially connected between a first supply voltage terminal and said second output of the pre-driver stage, a node between said first pair of transistors being connected to said first output of the pre-driver stage; and a second pair of transistors being serially connected between said first output of the pre-driver stage and a second supply voltage terminal, a node between said second pair of transistors being connected to said second output of the pre-driver stage.

Claim 5

An output buffer circuit according to claim 3 wherein control electrodes of said first and second pairs of transistors are connected to the input stage outputs.

Claim 6

An output buffer circuit according to claim 4 wherein said first pair of transistors are MOS transistors of a first conductivity, and said second pair of transistors are MOS transistors of a second conductivity.

Claim 7

An output buffer circuit according to claim 5 wherein said first conductivity is a p-type conductivity, and said second conductivity is an n-conductivity.

Claim 8

An output buffer circuit according to claim 3 wherein: said first predetermined controlled delay period is determined by width-to-length ratios (W/L) of said second pair of transistors; and said second predetermined controlled delay period is determined by width-to-length ratios (W/L) of said first pair of transistors.

Claim 9

An output buffer circuit according to claim 1 wherein: said at least one complementary pair of output transistor devices comprises a p-channel MOS transistor and an n-channel MOS transistor.

Claim 10

An output buffer circuit according to claim 8 wherein: a source of said p-channel MOS transistor is connected to a first supply voltage terminal; a gate of said p-channel MOS transistor receives said first output from the pre-driver stage; drain electrodes of both of said p-channel and n-channel MOS transistors are connected together for providing the output signal; a gate of said n-channel MOS transistor receives the second output from the pre-driver stage; and a source of said n-channel transistor is connected to a second supply voltage terminal.

Claim 11

An output buffer circuit having a data input terminal for receiving a data signal, and an output signal terminal for providing an output signal, comprising: an input stage for receiving the data signal from the data input terminal and for providing input stage outputs; a pre-driver stage for receiving the input stage outputs and for providing first and second outputs in response to the input stage outputs, said first output becoming logically low at a first predetermined controlled delay period after said second output becomes logically low, and said second output becoming logically high at a second predetermined controlled delay period after said first output becomes logically high; an output driver stage including a plurality of complementary pairs of serially connected p- and n-channel MOS transistors, said plurality of pairs being connected in parallel between first and second supply voltage terminals, control electrodes of said p-channel transistors receiving said first output from the pre-driver stage, control electrodes of said n-channel transistors receiving said second output from the pre-driver stage, and all nodes between said MOS transistors in said pairs being connected together for providing the output signal to the output signal terminal; and assist means for receiving the input stage outputs and for assisting said MOS transistors in turning off, said first and second outputs of the pre-driver stage being supplied only to said output driver stage and not to said input stage.

Claim 12

An output buffer circuit having a data input terminal for receiving a data signal, and an output signal terminal for providing an output signal, comprising: an input stage for receiving the data signal from the data input terminal and for providing input stage outputs; a pre-driver stage for receiving the input stage outputs and for providing first and second outputs in response to the input stage outputs, said first output becoming logically low at a first predetermined controlled delay period after said second output becomes logically low, and said second output becoming logically high at a second predetermined controlled delay period after said first output becomes logically high; an output driver stage including a plurality of complementary pairs of serially connected p- and n-channel MOS transistors, said plurality of pairs being connected in parallel between first and second supply voltage terminals, control electrodes of said p-channel transistors receiving said first output from the pre-driver stage, control electrodes of said n-channel transistors receiving said second output from the pre-driver stage, and all nodes between said MOS transistors in said pairs being connected together for providing the output signal to the output signal terminal; and assist means for receiving the input stage outputs and for assisting said MOS transistors in turning off, said first and second outputs of the pre-driver stage being supplied only to said output driver stage and not to said input stage.

Claim 13

An output buffer circuit according to claim 10 wherein: said input stage comprises a first logic gate and a second logic gate each having at least one input and an output, said inputs of the first and second logic gates being connected in common for receiving the data signal.

Claim 14

An output buffer circuit according to claim 10 wherein said pre-driver stage comprises: a first pair of transistors being serially connected between a first voltage supply and said second output of the pre-driver stage, a node between said first pair of transistors being connected to said first output of the pre-driver stage; and a second pair of transistors being serially connected between said first output of the pre-driver stage and a second voltage supply, a node between said second pair of transistors being connected to said second output of the pre-driver stage.

Claim 15

An output buffer circuit according to claim 12 wherein: said assist means further comprise MOS transistors having gates connected to the input stage outputs, said assist means supplying signals for turning off the MOS transistors in the output driver stage.

Claim 16

An output buffer circuit according to claim 12 wherein: said first predetermined controlled delay period is determined by width-to-length ratios (W/L) of said second pair of transistors; and said second predetermined controlled delay period is determined by width-to-length ratios (W/L) of said first pair of transistors.